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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gWOPx-0008KE-5L; Mon, 10 Dec 2018 16:28:25 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gWOG7-0007jy-08 for linux-arm-kernel@lists.infradead.org; Mon, 10 Dec 2018 16:18:23 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 834D81596; Mon, 10 Dec 2018 08:18:04 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 536D53F6A8; Mon, 10 Dec 2018 08:18:04 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 013211AE0B8F; Mon, 10 Dec 2018 16:18:26 +0000 (GMT) Date: Mon, 10 Dec 2018 16:18:26 +0000 From: Will Deacon To: Steve Capper Subject: Re: [PATCH V5 5/7] arm64: mm: Prevent mismatched 52-bit VA support Message-ID: <20181210161826.GA11135@edgewater-inn.cambridge.arm.com> References: <20181206225042.11548-1-steve.capper@arm.com> <20181206225042.11548-6-steve.capper@arm.com> <81860712-ff5f-5a51-d39e-9db9e3d31a26@arm.com> <20181207152529.GB2682@edgewater-inn.cambridge.arm.com> <20181210133640.GA31425@edgewater-inn.cambridge.arm.com> <20181210160348.GA4564@capper-debian.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20181210160348.GA4564@capper-debian.cambridge.arm.com> User-Agent: Mutt/1.11.1+30 (d10eec459b35) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181210_081815_312761_BC5EB333 X-CRM114-Status: GOOD ( 25.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org" , Catalin Marinas , Suzuki Poulose , "linux-mm@kvack.org" , "jcm@redhat.com" , nd , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Dec 10, 2018 at 04:04:02PM +0000, Steve Capper wrote: > On Mon, Dec 10, 2018 at 01:36:40PM +0000, Will Deacon wrote: > > On Fri, Dec 07, 2018 at 05:28:58PM +0000, Suzuki K Poulose wrote: > > > On 07/12/2018 15:26, Will Deacon wrote: > > > > On Fri, Dec 07, 2018 at 10:47:57AM +0000, Suzuki K Poulose wrote: > > > > > On 12/06/2018 10:50 PM, Steve Capper wrote: > > > > > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > > > > > > index f60081be9a1b..58fcc1edd852 100644 > > > > > > --- a/arch/arm64/kernel/head.S > > > > > > +++ b/arch/arm64/kernel/head.S > > > > > > @@ -707,6 +707,7 @@ secondary_startup: > > > > > > /* > > > > > > * Common entry point for secondary CPUs. > > > > > > */ > > > > > > + bl __cpu_secondary_check52bitva > > > > > > bl __cpu_setup // initialise processor > > > > > > adrp x1, swapper_pg_dir > > > > > > bl __enable_mmu > > > > > > @@ -785,6 +786,31 @@ ENTRY(__enable_mmu) > > > > > > ret > > > > > > ENDPROC(__enable_mmu) > > > > > > +ENTRY(__cpu_secondary_check52bitva) > > > > > > +#ifdef CONFIG_ARM64_52BIT_VA > > > > > > + ldr_l x0, vabits_user > > > > > > + cmp x0, #52 > > > > > > + b.ne 2f > + > > > > > > + mrs_s x0, SYS_ID_AA64MMFR2_EL1 > > > > > > + and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT) > > > > > > + cbnz x0, 2f > > > > > > + > > > > > > + adr_l x0, va52mismatch > > > > > > + mov w1, #1 > > > > > > + strb w1, [x0] > > > > > > + dmb sy > > > > > > + dc ivac, x0 // Invalidate potentially stale cache line > > > > > > > > > > You may have to clear this variable before a CPU is brought up to avoid > > > > > raising a false error message when another secondary CPU doesn't boot > > > > > for some other reason (say granule support) after a CPU failed with lack > > > > > of 52bitva. It is really a crazy corner case. > > > > > > > > Can't we just follow the example set by the EL2 setup in the way that is > > > > uses __boot_cpu_mode? In that case, we only need one variable and you can > > > > detect a problem by comparing the two halves. > > > > > > The only difference here is, the support is bolted at boot CPU time and hence > > > we need to verify each and every CPU, unlike the __boot_cpu_mode where we > > > check for mismatch after the SMP CPUs are brought up. If we decide to make > > > the choice later, something like that could work. The only caveat is the 52bit > > > kernel VA will have to do something like the above. > > > > So looking at this a bit more, I think we're better off repurposing the > > upper bits of the early boot status word to contain a reason code, rather > > than introducing new variables for every possible mismatch. > > > > Does the untested diff below look remotely sane to you? > > > > Will > > > > Thanks Will, > This looks good to me, I will test now and fold this into a patch. Cheers, Steve. Testing would be handy, but don't worry about respinning the patches as I'm already on top of this and hope to push this out later today. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel