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Tue, 11 Dec 2018 11:15:14 +0200 (EET) Date: Tue, 11 Dec 2018 11:15:14 +0200 From: Peter De Schrijver To: Jon Hunter Subject: Re: [PATCH 01/19] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Message-ID: <20181211091514.GA29064@pdeschrijver-desktop.Nvidia.com> References: <20181204092548.3038-1-josephl@nvidia.com> <20181204092548.3038-2-josephl@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-NVConfidentiality: public User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL108.nvidia.com (172.18.146.13) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544519715; bh=JtRcGU7uSLlDQHzVE/5xrx7U9Pn2qELtrHn9KxpN8jc=; h=X-PGP-Universal:Date:From:To:CC:Subject:Message-ID:References: MIME-Version:Content-Type:Content-Disposition:In-Reply-To: X-NVConfidentiality:User-Agent:X-Originating-IP:X-ClientProxiedBy; b=fGpDwENdzpBhTq0uThDCLcf91NWv6BUQSKdXKJhhzCTZhOVVM9fbIwftZAN8DVSWU iO2gVZxakPYeWOQbrpqtqSF1BiA+cVzobez1f/Wit4LyKZfRQHgFV8OxY066SjU9UK KZaPYzBWEjV8YB6Y/xDxjioJfkUHoUKq99tBuBIKw6w+xhHENNAVXWEc6YIqWqJOmk Wo2gHNnwqdmpDSsAJcZzwq1e0IaKZlKS+XNMpBagJ0UHUiuuICtyNKsUbHKKywInX9 /fZ6iEAxCroJKyInsPkcfSea1+BB14nzvCgOawNzoj9wfvmztAoB1d/QPs7C1E2Mk6 lRzh2vOekFH9w== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181211_011528_100442_DA5A0AB0 X-CRM114-Status: GOOD ( 20.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Thierry Reding , Joseph Lo , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 07, 2018 at 01:41:57PM +0000, Jon Hunter wrote: > > On 04/12/2018 09:25, Joseph Lo wrote: > > From: Peter De Schrijver > > > > Add new properties to configure the DFLL PWM regulator support. Also > > add an example and make the I2C clock only required when I2C support is > > used. > > > > Cc: devicetree@vger.kernel.org > > Signed-off-by: Peter De Schrijver > > Signed-off-by: Joseph Lo > > --- > > .../bindings/clock/nvidia,tegra124-dfll.txt | 73 ++++++++++++++++++- > > 1 file changed, 71 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt > > index dff236f524a7..8c97600d2bad 100644 > > --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt > > +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt > > @@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running voltage controlled > > oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop > > control module that will automatically adjust the VDD_CPU voltage by > > communicating with an off-chip PMIC either via an I2C bus or via PWM signals. > > -Currently only the I2C mode is supported by these bindings. > > > > Required properties: > > - compatible : should be "nvidia,tegra124-dfll" > > @@ -45,10 +44,28 @@ Required properties for the control loop parameters: > > Optional properties for the control loop parameters: > > - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. > > > > +Optional properties for mode selection: > > +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C. > > + > > Required properties for I2C mode: > > - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. > > > > -Example: > > +Required properties for PWM mode: > > +- nvidia,pwm-period: period of PWM square wave in microseconds. > > +- nvidia,init-uv: Regulator voltage in micro volts when PWM control is disabled. > > Maybe consider 'pwm-inactive-voltage-microvolt'. > Inactive is not very accurate. The OVR regulator will output nvidia,align-offset-uv when the PWM input is driven low but will output nvidia,init-uv when the PWM input is in tristate mode. > > +- nvidia,align-offset-uv: Regulator voltage in micro volts when PWM control is > > + enabled and PWM output is low. > > Would this be considered the minimum pwm active voltage? > > > +- nvidia,align-step-uv: Voltage increase in micro volts corresponding to a > > + 1/33th increase in duty cycle. Eg the voltage for 2/33th > > + duty cycle would be: > > Maybe consider 'pwm-voltage-step-microvolt'. > > > + nvidia,align-offset-uv + nvidia,align-step-uv * 2. > > +- pinctrl-0: I/O pad configuration when PWM control is enabled. > > +- pinctrl-1: I/O pad configuration when PWM control is disabled. > > +- pinctrl-names: must include the following entries: > > + - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. > > + - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. > > Please see Rob's feedback on the above [0]. > > Cheers > Jon > > [0] https://lore.kernel.org/patchwork/patch/885328/ > > -- > nvpublic _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel