From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78755C04EB8 for ; Wed, 12 Dec 2018 14:39:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3AED720839 for ; Wed, 12 Dec 2018 14:39:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="DXvztLfY" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3AED720839 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=H0RXOCZgRx2U1hPMgY8p4vYIec4nCQX/wQ9s+SqfpsU=; b=DXvztLfY/1sdgf hotp/sEyI8+Akqf5xESHNPSbYHw9/fLW682TQeSGGtfWTbBYzuFOlQYg5OhWtE5NzhfQw6UkbiBDq mHo2v5aTOxSjQd85FuYZSn/QtLL/1Wbb0AmncKmyl8zcpAsMCRKkafX7Lo0SmGkVX8J60/DCelgn3 Mg8kxbkeaOdN39X8PCIoMdNTeZKzCCdI0VNuU7nUQ7IXE/HBySdjvX7+cFLB5Uld9fjSa0HH/J06t 9vusDOmR14V/P0B+OqbEeAoNuxexNo+PFQJKvONxUxsrDYBfByfOJJ6dU0SKJ6IYOkZk5E91Ikzz3 8eIvtBNxDnn22ISakJhg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gX5eu-0005qB-K6; Wed, 12 Dec 2018 14:38:44 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gX5er-0005pY-T1 for linux-arm-kernel@lists.infradead.org; Wed, 12 Dec 2018 14:38:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57E4280D; Wed, 12 Dec 2018 06:38:26 -0800 (PST) Received: from localhost (unknown [10.37.6.11]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B48823F59C; Wed, 12 Dec 2018 06:38:25 -0800 (PST) Date: Wed, 12 Dec 2018 14:38:23 +0000 From: Andrew Murray To: Suzuki K Poulose Subject: Re: [PATCH v8 4/5] arm64: arm_pmu: Add support for exclude_host/exclude_guest attributes Message-ID: <20181212143823.GA48249@e119886-lin.cambridge.arm.com> References: <1544610573-28446-5-git-send-email-andrew.murray@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181212_063841_951791_5AE5F6BE X-CRM114-Status: GOOD ( 22.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Julien Thierry , Marc Zyngier , Catalin Marinas , Will Deacon , Christoffer Dall , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 12, 2018 at 10:55:33AM +0000, Suzuki K Poulose wrote: > > > On 12/12/2018 10:29, Andrew Murray wrote: > > Add support for the :G and :H attributes in perf by handling the > > exclude_host/exclude_guest event attributes. > > > > We notify KVM of counters that we wish to be enabled or disabled on > > guest entry/exit and thus defer from starting or stopping :G events > > as per the events exclude_host attribute. > > > > With both VHE and non-VHE we switch the counters between host/guest > > at EL2. We are able to eliminate counters counting host events on > > the boundaries of guest entry/exit when using :G by filtering out > > EL2 for exclude_host. However when using :H unless exclude_hv is set > > on non-VHE then there is a small blackout window at the guest > > entry/exit where host events are not captured. > > > > Signed-off-by: Andrew Murray > > --- > > arch/arm64/kernel/perf_event.c | 51 ++++++++++++++++++++++++++++++++++++------ > > 1 file changed, 44 insertions(+), 7 deletions(-) > > > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > > index de564ae..4a3c73d 100644 > > --- a/arch/arm64/kernel/perf_event.c > > +++ b/arch/arm64/kernel/perf_event.c > > @@ -26,6 +26,7 @@ > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -647,11 +648,26 @@ static inline int armv8pmu_enable_counter(int idx) > > static inline void armv8pmu_enable_event_counter(struct perf_event *event) > > { > > + struct perf_event_attr *attr = &event->attr; > > int idx = event->hw.idx; > > + int flags = 0; > > + u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); > > - armv8pmu_enable_counter(idx); > > if (armv8pmu_event_is_chained(event)) > > - armv8pmu_enable_counter(idx - 1); > > + counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); > > + > > + if (!attr->exclude_host) > > + flags |= KVM_PMU_EVENTS_HOST; > > + if (!attr->exclude_guest) > > + flags |= KVM_PMU_EVENTS_GUEST; > > + > > + kvm_set_pmu_events(counter_bits, flags); > > + > > + if (!attr->exclude_host) { > > + armv8pmu_enable_counter(idx); > > + if (armv8pmu_event_is_chained(event)) > > + armv8pmu_enable_counter(idx - 1); > > + } > > } > > static inline int armv8pmu_disable_counter(int idx) > > @@ -664,11 +680,20 @@ static inline int armv8pmu_disable_counter(int idx) > > static inline void armv8pmu_disable_event_counter(struct perf_event *event) > > { > > struct hw_perf_event *hwc = &event->hw; > > + struct perf_event_attr *attr = &event->attr; > > int idx = hwc->idx; > > + u32 counter_bits = BIT(ARMV8_IDX_TO_COUNTER(idx)); > > if (armv8pmu_event_is_chained(event)) > > - armv8pmu_disable_counter(idx - 1); > > - armv8pmu_disable_counter(idx); > > + counter_bits |= BIT(ARMV8_IDX_TO_COUNTER(idx - 1)); > > + > > + kvm_clr_pmu_events(counter_bits); > > + > > + if (!attr->exclude_host) { > > + if (armv8pmu_event_is_chained(event)) > > + armv8pmu_disable_counter(idx - 1); > > + armv8pmu_disable_counter(idx); > > + } > > It may be helpful to add in a comment why we do this only for !exclude_host. > > Either way, No problem, I'll add the comments. > > Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel