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Fri, 14 Dec 2018 06:15:40 -0800 (PST) Date: Fri, 14 Dec 2018 09:15:39 -0500 From: Sean Paul To: Jagan Teki Subject: Re: [PATCH v2 11/12] drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel Message-ID: <20181214141539.GN154160@art_vandelay> References: <20181116163916.29621-1-jagan@amarulasolutions.com> <20181116163916.29621-12-jagan@amarulasolutions.com> <20181213150736.GL154160@art_vandelay> <20181213194804.GM154160@art_vandelay> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181214_061552_490626_E1006FF7 X-CRM114-Status: GOOD ( 30.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree , Jernej Skrabec , Maxime Ripard , linux-amarula@amarulasolutions.com, linux-sunxi , Maarten Lankhorst , linux-kernel , dri-devel , Vasily Khoruzhick , David Airlie , Chen-Yu Tsai , Rob Herring , Thierry Reding , TL Lim , Michael Trimarchi , Sean Paul , linux-arm-kernel , Icenowy Zheng Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 14, 2018 at 04:35:11PM +0530, Jagan Teki wrote: > On Fri, Dec 14, 2018 at 1:25 AM Sean Paul wrote: > > > > On Fri, Dec 14, 2018 at 12:56:03AM +0530, Jagan Teki wrote: > > > On Thu, Dec 13, 2018 at 8:37 PM Sean Paul wrote: > > > > > > > > On Fri, Nov 16, 2018 at 10:09:15PM +0530, Jagan Teki wrote: > > > > > Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel. > > > > > > > > > > Add panel driver for it. > > > > > > > > > > Signed-off-by: Jagan Teki > > > > > --- > > > > > MAINTAINERS | 6 + > > > > > drivers/gpu/drm/panel/Kconfig | 9 + > > > > > drivers/gpu/drm/panel/Makefile | 1 + > > > > > .../drm/panel/panel-feiyang-fy07024di26a30d.c | 286 ++++++++++++++++++ > > > > > 4 files changed, 302 insertions(+) > > > > > create mode 100644 drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > > > > > > > > > /snip > > > > > > > diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > > > > > new file mode 100644 > > > > > index 000000000000..a4b46bd8fdbe > > > > > --- /dev/null > > > > > +++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c > > > > /snip > > > > > > > +static int feiyang_prepare(struct drm_panel *panel) > > > > > +{ > > > > > + struct feiyang *ctx = panel_to_feiyang(panel); > > > > > + struct mipi_dsi_device *dsi = ctx->dsi; > > > > > + unsigned int i; > > > > > + int ret; > > > > > + > > > > > + ret = regulator_enable(ctx->dvdd); > > > > > + if (ret) > > > > > + return ret; > > > > > + > > > > > + msleep(100); > > > > > > > > nit: You should do your best to correlate the sleeps with the timing parameters > > > > from the datasheet with a comment. > > > > > > > > ie: > > > > /* T1: > 100ms */ > > > > msleep(100); > > > > > > Sorry, what does this mean? > > > > On page 9 of the datasheet you sent me [1], it has the delays required to safely > > power up the panel. This delay is the time between dvdd going high and avdd > > going high. On the figure in the datasheet, this would be T2 (T1 is dvdd rise > > time between dvdd going high and avdd going high is T1 + T3 right? > > T2 > 0ms > T3 > 20ms > > In this case the delay can be msleep(20) ? Hmm, yeah, I didn't notice that T3 was > 20ms, that's kind of confusing. So I think you're right, this should be T2 + T3 > 20ms (T1 is covered in the regulator_enable of dvdd). > > > time and should be handled in the regulator subsystem (iirc)). Also according to > > the datasheet, T2 just needs to be > 0, so you don't even need this delay. You > > could replace this with a comment like: > > > > /* T1 (dvdd rise time) + T2 (dvdd->avdd) > 0 */ > > > > So for all of the msleeps below you should get the delays from the datasheet and > > add a comment referencing them. > > T5 and T6 are delay between avdd to reset enable it can be 10 + 10 > => 20ms and finally T12 which is 200 after reset. > > What about the delay between resets, I need to understand it a bit. These are usually accounted for at the end of disable. Take a look at the sleep parameters in panel-simple for an example. Sean -- Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel