From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: linux-arm-kernel@lists.infradead.org
Cc: marc.zyngier@arm.com, Ard Biesheuvel <ard.biesheuvel@linaro.org>,
christoffer.dall@arm.com, Suzuki.Poulose@arm.com
Subject: [RFC PATCH 0/2] arm64: kvm: cache ID register trapping
Date: Mon, 17 Dec 2018 16:02:03 +0100 [thread overview]
Message-ID: <20181217150205.27981-1-ard.biesheuvel@linaro.org> (raw)
While looking into whether we could report the cache geometry as 1 set
and 1 way so that the ARM kernel doesn't stall for 13 seconds at boot,
I noticed that we don't expose the sanitised version of CTR_EL0 to guests,
so I fixed that first (#1)
Since that gives us most of the groundwork for overriding the cache
geometry, it is a fairly trivial change (#2) to clear the set/way
fields in the CCSIDR register so that it describes 1 set and 1 way.
Notes:
- build tested only
- 64-bit hosts only.
Ard Biesheuvel (2):
arm64: kvm: expose sanitised cache type register to guest
arm64: kvm: describe data or unified caches as having 1 set and 1 way
arch/arm64/include/asm/kvm_arm.h | 3 +-
arch/arm64/include/asm/sysreg.h | 1 +
arch/arm64/kvm/sys_regs.c | 74 +++++++++++++++++++-
3 files changed, 75 insertions(+), 3 deletions(-)
--
2.17.1
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next reply other threads:[~2018-12-17 15:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-17 15:02 Ard Biesheuvel [this message]
2018-12-17 15:02 ` [RFC PATCH 1/2] arm64: kvm: expose sanitised cache type register to guest Ard Biesheuvel
2019-01-31 11:22 ` Marc Zyngier
2019-01-31 11:24 ` Ard Biesheuvel
2019-01-31 11:44 ` Marc Zyngier
2019-01-31 11:45 ` Ard Biesheuvel
2018-12-17 15:02 ` [RFC PATCH 2/2] arm64: kvm: describe data or unified caches as having 1 set and 1 way Ard Biesheuvel
2019-01-08 11:02 ` Christoffer Dall
2019-01-08 11:11 ` Ard Biesheuvel
2019-01-08 11:14 ` Christoffer Dall
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