From: Rob Herring <robh@kernel.org>
To: Joseph Lo <josephl@nvidia.com>
Cc: devicetree@vger.kernel.org,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>,
linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V3 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator
Date: Tue, 18 Dec 2018 09:19:34 -0600 [thread overview]
Message-ID: <20181218151934.GA10127@bogus> (raw)
In-Reply-To: <20181218091232.23532-2-josephl@nvidia.com>
On Tue, Dec 18, 2018 at 05:12:13PM +0800, Joseph Lo wrote:
> From: Peter De Schrijver <pdeschrijver@nvidia.com>
>
> Add new properties to configure the DFLL PWM regulator support.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> *V3:
> - no change
> *V2:
> - update the binding strings and descriptions for
> nvidia,pwm-tristate-microvolts
> nvidia,pwm-min-microvolts
> nvidia,pwm-voltage-step-microvolts
> ---
> .../bindings/clock/nvidia,tegra124-dfll.txt | 79 ++++++++++++++++++-
> 1 file changed, 77 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> index dff236f524a7..38e8cc8c70a8 100644
> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> @@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running voltage controlled
> oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
> control module that will automatically adjust the VDD_CPU voltage by
> communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
> -Currently only the I2C mode is supported by these bindings.
>
> Required properties:
> - compatible : should be "nvidia,tegra124-dfll"
> @@ -45,10 +44,31 @@ Required properties for the control loop parameters:
> Optional properties for the control loop parameters:
> - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
>
> +Optional properties for mode selection:
> +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
> +
> Required properties for I2C mode:
> - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
>
> -Example:
> +Required properties for PWM mode:
> +- nvidia,pwm-period: period of PWM square wave in microseconds.
Needs unit suffix.
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next prev parent reply other threads:[~2018-12-18 15:19 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-18 9:12 [PATCH V3 00/20] Tegra210 DFLL support Joseph Lo
2018-12-18 9:12 ` [PATCH V3 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-18 9:56 ` Jon Hunter
2018-12-18 15:19 ` Rob Herring [this message]
2018-12-19 7:04 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-18 15:44 ` Rob Herring
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-18 15:45 ` Rob Herring
2018-12-18 9:12 ` [PATCH V3 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-18 15:47 ` Rob Herring
2018-12-18 9:12 ` [PATCH V3 05/20] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-18 9:58 ` Jon Hunter
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 07/20] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-18 10:00 ` Jon Hunter
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 08/20] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-18 10:05 ` Jon Hunter
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 09/20] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-18 10:05 ` Jon Hunter
2018-12-18 18:42 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-18 18:00 ` Stephen Boyd
2018-12-19 7:08 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 11/20] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-18 9:37 ` Rafael J. Wysocki
2018-12-19 6:24 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 12/20] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-18 9:12 ` [PATCH V3 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2018-12-18 9:12 ` [PATCH V3 14/20] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-18 9:12 ` [PATCH V3 15/20] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-18 9:12 ` [PATCH V3 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-18 9:12 ` [PATCH V3 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-18 9:12 ` [PATCH V3 18/20] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-18 9:12 ` [PATCH V3 19/20] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-18 9:12 ` [PATCH V3 20/20] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
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