From: Harald Geyer <harald@ccbib.org>
To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Harald Geyer <harald@ccbib.org>,
linux-arm-kernel@lists.infradead.org,
Rob Herring <robh@kernel.org>
Subject: [PATCH] arm64: dts: allwinner: a64: Add PMU node
Date: Wed, 19 Dec 2018 15:40:17 +0000 [thread overview]
Message-ID: <20181219154017.6104-1-harald@ccbib.org> (raw)
This is necessary to use 'perf' for cache profiling etc.
Tested on Teres I Laptop.
Signed-off-by: Harald Geyer <harald@ccbib.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 837a03dee875..bf9b719481c4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -142,6 +142,15 @@
clock-output-names = "ext-osc32k";
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
psci {
compatible = "arm,psci-0.2";
method = "smc";
--
2.11.0
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next reply other threads:[~2018-12-19 15:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-19 15:40 Harald Geyer [this message]
2018-12-19 15:47 ` [PATCH] arm64: dts: allwinner: a64: Add PMU node Maxime Ripard
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