[PATCH] clk: imx8mq: Add dsi_ipg_div

[PATCH] clk: imx8mq: Add dsi_ipg_div

[Guido Günther]

It's defined imx8mq-clock.h but wasn't assigned yet.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
---
I'm not sure I picked the intended clock type but it gives me the right
clock rate.

 drivers/clk/imx/clk-imx8mq.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 398ab0bcd9de..6f082153714e 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -485,6 +485,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	clks[IMX8MQ_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
 	clks[IMX8MQ_CLK_DSI_ESC] = imx8m_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
 	clks[IMX8MQ_CLK_DSI_AHB] = imx8m_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
+	clks[IMX8MQ_CLK_DSI_IPG_DIV] = imx_clk_divider2("dsi_ipg_div", "dsi_ahb", base + 0x9280, 0, 6);
 	clks[IMX8MQ_CLK_CSI1_CORE] = imx8m_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
 	clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
 	clks[IMX8MQ_CLK_CSI1_ESC] = imx8m_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);
-- 
2.20.1

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Re: [PATCH] clk: imx8mq: Add dsi_ipg_div

[Guido Günther]

Hi,
On Tue, Jan 15, 2019 at 05:38:23PM +0100, Guido Günther wrote:
> It's defined imx8mq-clock.h but wasn't assigned yet.

I've found these additional unassigned clocks (defined in
include/dt-bindings/clock/imx8mq-clock.h but not assigned in
drivers/clk/imx/clk-imx8mq.c):

IMX8MQ_CLK_A53_ROOT 
IMX8MQ_CLK_DRAM_ROOT
IMX8MQ_CLK_HEVC_ROOT
IMX8MQ_CLK_AVC_ROOT
IMX8MQ_CLK_VP9_ROOT
IMX8MQ_CLK_HEVC_INTER_ROOT
IMX8MQ_CLK_HDMI_ROOT
IMX8MQ_CLK_HDMI_PHY_ROOT
IMX8MQ_VIDEO2_PLL_OUT
IMX8MQ_CLK_M4_ROOT
IMX8MQ_CLK_M4_SRC
IMX8MQ_CLK_M4_CG
IMX8MQ_CLK_M4_DIV

I can look into adding these but just wanted to make sure they're not
sitting in a tree already.

Cheers,
 -- Guido

> Signed-off-by: Guido Günther <agx@sigxcpu.org>
> ---
> I'm not sure I picked the intended clock type but it gives me the right
> clock rate.
> 
>  drivers/clk/imx/clk-imx8mq.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 398ab0bcd9de..6f082153714e 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -485,6 +485,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
>  	clks[IMX8MQ_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mq_dsi_dbi_sels, base + 0xbc00);
>  	clks[IMX8MQ_CLK_DSI_ESC] = imx8m_clk_composite("dsi_esc", imx8mq_dsi_esc_sels, base + 0xbc80);
>  	clks[IMX8MQ_CLK_DSI_AHB] = imx8m_clk_composite("dsi_ahb", imx8mq_dsi_ahb_sels, base + 0x9200);
> +	clks[IMX8MQ_CLK_DSI_IPG_DIV] = imx_clk_divider2("dsi_ipg_div", "dsi_ahb", base + 0x9280, 0, 6);
>  	clks[IMX8MQ_CLK_CSI1_CORE] = imx8m_clk_composite("csi1_core", imx8mq_csi1_core_sels, base + 0xbd00);
>  	clks[IMX8MQ_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mq_csi1_phy_sels, base + 0xbd80);
>  	clks[IMX8MQ_CLK_CSI1_ESC] = imx8m_clk_composite("csi1_esc", imx8mq_csi1_esc_sels, base + 0xbe00);
> -- 
> 2.20.1

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