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Tue, 22 Jan 2019 11:00:48 -0800 (PST) Date: Tue, 22 Jan 2019 14:00:48 -0500 From: Sean Paul To: Stephen Boyd Subject: Re: [PATCH] drm/msm/dpu: Convert to a chained irq chip Message-ID: <20190122190048.GE114153@art_vandelay> References: <20190103190602.92612-1-swboyd@chromium.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190103190602.92612-1-swboyd@chromium.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190122_110051_350367_658A841B X-CRM114-Status: GOOD ( 23.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Crouse , Rajesh Yadav , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Jayant Shekhar , Rob Clark , Sean Paul , Jeykumar Sankaran , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 03, 2019 at 11:06:02AM -0800, Stephen Boyd wrote: > Devices that make up DPU, i.e. graphics card, request their interrupts > from this "virtual" interrupt chip. The interrupt chip builds upon a GIC > SPI interrupt that raises high when any of the interrupts in the DPU's > irq status register are triggered. From the kernel's perspective this is > a chained irq chip, so requesting a flow handler for the GIC SPI and > then calling generic IRQ handling code from that irq handler is not > completely proper. It's better to convert this to a chained irq so that > the GIC SPI irq doesn't appear in /proc/interrupts, can't have CPU > affinity changed, and won't be accounted for with irq stats. Doing this > also silences a recursive lockdep warning because we can specify a > different lock class for the chained interrupts, silencing a warning > that is easy to see with 'threadirqs' on the kernel commandline. > > WARNING: inconsistent lock state > 4.19.10 #76 Tainted: G W > -------------------------------- > inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. > irq/40-dpu_mdss/203 [HC0[0]:SC0[2]:HE1:SE0] takes: > 0000000053ea9021 (&irq_desc_lock_class){?.-.}, at: handle_level_irq+0x34/0x26c > {IN-HARDIRQ-W} state was registered at: > lock_acquire+0x244/0x360 > _raw_spin_lock+0x64/0xa0 > handle_fasteoi_irq+0x54/0x2ec > generic_handle_irq+0x44/0x5c > __handle_domain_irq+0x9c/0x11c > gic_handle_irq+0x208/0x260 > el1_irq+0xb4/0x130 > arch_cpu_idle+0x178/0x3cc > default_idle_call+0x3c/0x54 > do_idle+0x1a8/0x3dc > cpu_startup_entry+0x24/0x28 > rest_init+0x240/0x270 > start_kernel+0x5a8/0x6bc > irq event stamp: 18 > hardirqs last enabled at (17): [] _raw_spin_unlock_irq+0x40/0xc0 > hardirqs last disabled at (16): [] __schedule+0x20c/0x1bbc > softirqs last enabled at (0): [] copy_process+0xb50/0x3964 > softirqs last disabled at (18): [] local_bh_disable+0x8/0x20 > > other info that might help us debug this: > Possible unsafe locking scenario: > > CPU0 > ---- > lock(&irq_desc_lock_class); > > lock(&irq_desc_lock_class); > > *** DEADLOCK *** > > no locks held by irq/40-dpu_mdss/203. > > stack backtrace: > CPU: 0 PID: 203 Comm: irq/40-dpu_mdss Tainted: G W 4.19.10 #76 > Call trace: > dump_backtrace+0x0/0x2f8 > show_stack+0x20/0x2c > __dump_stack+0x20/0x28 > dump_stack+0xcc/0x10c > mark_lock+0xbe0/0xe24 > __lock_acquire+0x4cc/0x2708 > lock_acquire+0x244/0x360 > _raw_spin_lock+0x64/0xa0 > handle_level_irq+0x34/0x26c > generic_handle_irq+0x44/0x5c > dpu_mdss_irq+0x64/0xec > irq_forced_thread_fn+0x58/0x9c > irq_thread+0x120/0x1dc > kthread+0x248/0x260 > ret_from_fork+0x10/0x18 > ------------[ cut here ]------------ > irq 169 handler irq_default_primary_handler+0x0/0x18 enabled interrupts > > Cc: Sean Paul > Cc: Jordan Crouse > Cc: Jayant Shekhar > Cc: Rajesh Yadav > Cc: Jeykumar Sankaran > Signed-off-by: Stephen Boyd LGTM, applied to dpu-staging. Thanks, Sean > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 36 ++++++++++++++---------- > 1 file changed, 21 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c > index cb307a2abf06..7316b4ab1b85 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c > @@ -23,11 +23,14 @@ struct dpu_mdss { > struct dpu_irq_controller irq_controller; > }; > > -static irqreturn_t dpu_mdss_irq(int irq, void *arg) > +static void dpu_mdss_irq(struct irq_desc *desc) > { > - struct dpu_mdss *dpu_mdss = arg; > + struct dpu_mdss *dpu_mdss = irq_desc_get_handler_data(desc); > + struct irq_chip *chip = irq_desc_get_chip(desc); > u32 interrupts; > > + chained_irq_enter(chip, desc); > + > interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS); > > while (interrupts) { > @@ -39,20 +42,20 @@ static irqreturn_t dpu_mdss_irq(int irq, void *arg) > hwirq); > if (mapping == 0) { > DRM_ERROR("couldn't find irq mapping for %lu\n", hwirq); > - return IRQ_NONE; > + break; > } > > rc = generic_handle_irq(mapping); > if (rc < 0) { > DRM_ERROR("handle irq fail: irq=%lu mapping=%u rc=%d\n", > hwirq, mapping, rc); > - return IRQ_NONE; > + break; > } > > interrupts &= ~(1 << hwirq); > } > > - return IRQ_HANDLED; > + chained_irq_exit(chip, desc); > } > > static void dpu_mdss_irq_mask(struct irq_data *irqd) > @@ -83,16 +86,16 @@ static struct irq_chip dpu_mdss_irq_chip = { > .irq_unmask = dpu_mdss_irq_unmask, > }; > > +static struct lock_class_key dpu_mdss_lock_key, dpu_mdss_request_key; > + > static int dpu_mdss_irqdomain_map(struct irq_domain *domain, > unsigned int irq, irq_hw_number_t hwirq) > { > struct dpu_mdss *dpu_mdss = domain->host_data; > - int ret; > > + irq_set_lockdep_class(irq, &dpu_mdss_lock_key, &dpu_mdss_request_key); > irq_set_chip_and_handler(irq, &dpu_mdss_irq_chip, handle_level_irq); > - ret = irq_set_chip_data(irq, dpu_mdss); > - > - return ret; > + return irq_set_chip_data(irq, dpu_mdss); > } > > static const struct irq_domain_ops dpu_mdss_irqdomain_ops = { > @@ -159,11 +162,13 @@ static void dpu_mdss_destroy(struct drm_device *dev) > struct msm_drm_private *priv = dev->dev_private; > struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss); > struct dss_module_power *mp = &dpu_mdss->mp; > + int irq; > > pm_runtime_suspend(dev->dev); > pm_runtime_disable(dev->dev); > _dpu_mdss_irq_domain_fini(dpu_mdss); > - free_irq(platform_get_irq(pdev, 0), dpu_mdss); > + irq = platform_get_irq(pdev, 0); > + irq_set_chained_handler_and_data(irq, NULL, NULL); > msm_dss_put_clk(mp->clk_config, mp->num_clk); > devm_kfree(&pdev->dev, mp->clk_config); > > @@ -187,6 +192,7 @@ int dpu_mdss_init(struct drm_device *dev) > struct dpu_mdss *dpu_mdss; > struct dss_module_power *mp; > int ret = 0; > + int irq; > > dpu_mdss = devm_kzalloc(dev->dev, sizeof(*dpu_mdss), GFP_KERNEL); > if (!dpu_mdss) > @@ -219,12 +225,12 @@ int dpu_mdss_init(struct drm_device *dev) > if (ret) > goto irq_domain_error; > > - ret = request_irq(platform_get_irq(pdev, 0), > - dpu_mdss_irq, 0, "dpu_mdss_isr", dpu_mdss); > - if (ret) { > - DPU_ERROR("failed to init irq: %d\n", ret); > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) > goto irq_error; > - } > + > + irq_set_chained_handler_and_data(irq, dpu_mdss_irq, > + dpu_mdss); > > pm_runtime_enable(dev->dev); > > -- > Sent by a computer through tubes > -- Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel