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* [PATCH] arm64: dts: imx8mq: Add ECSPI support
@ 2019-01-26 21:28 Fabio Estevam
  2019-01-27 21:34 ` Andrey Smirnov
  2019-01-28 10:36 ` Lucas Stach
  0 siblings, 2 replies; 3+ messages in thread
From: Fabio Estevam @ 2019-01-26 21:28 UTC (permalink / raw)
  To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, linux-imx, kernel

Add support for the three ECSPI ports present on i.MX8MQ.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 +++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 892063a7c26c..45b9d4a8b0da 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -26,6 +26,9 @@
 		serial1 = &uart2;
 		serial2 = &uart3;
 		serial3 = &uart4;
+		spi0 = &ecspi1;
+		spi1 = &ecspi2;
+		spi2 = &ecspi3;
 	};
 
 	ckil: clock-ckil {
@@ -381,6 +384,42 @@
 			#size-cells = <1>;
 			ranges = <0x30800000 0x30800000 0x400000>;
 
+			ecspi1: spi@30820000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+				reg = <0x0 0x30820000 0x0 0x10000>;
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
+					 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			ecspi2: spi@30830000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+				reg = <0x0 0x30830000 0x0 0x10000>;
+				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
+					 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			ecspi3: spi@30840000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
+				reg = <0x0 0x30840000 0x0 0x10000>;
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
+					 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
 			uart1: serial@30860000 {
 				compatible = "fsl,imx8mq-uart",
 				             "fsl,imx6q-uart";
-- 
2.17.1


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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: imx8mq: Add ECSPI support
  2019-01-26 21:28 [PATCH] arm64: dts: imx8mq: Add ECSPI support Fabio Estevam
@ 2019-01-27 21:34 ` Andrey Smirnov
  2019-01-28 10:36 ` Lucas Stach
  1 sibling, 0 replies; 3+ messages in thread
From: Andrey Smirnov @ 2019-01-27 21:34 UTC (permalink / raw)
  To: festevam
  Cc: Andrey Smirnov, linux-arm-kernel, kernel, shawnguo, cphealy,
	linux-imx

> Add support for the three ECSPI ports present on i.MX8MQ.
>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 +++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 892063a7c26c..45b9d4a8b0da 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -26,6 +26,9 @@
>  		serial1 = &uart2;
>  		serial2 = &uart3;
>  		serial3 = &uart4;
> +		spi0 = &ecspi1;
> +		spi1 = &ecspi2;
> +		spi2 = &ecspi3;
>  	};
>  
>  	ckil: clock-ckil {
> @@ -381,6 +384,42 @@
>  			#size-cells = <1>;
>  			ranges = <0x30800000 0x30800000 0x400000>;
>  
> +			ecspi1: spi@30820000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
> +				reg = <0x0 0x30820000 0x0 0x10000>;

AIPS3 in upstream tree uses #address-cells = <1> and size-cells = <1>,
so 'reg' property of this and other nodes needs to be adjusted for
that (vendor tree uses 2/2). With that small problem fixed:

Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Thanks,
Andrey Smirnov

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^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: imx8mq: Add ECSPI support
  2019-01-26 21:28 [PATCH] arm64: dts: imx8mq: Add ECSPI support Fabio Estevam
  2019-01-27 21:34 ` Andrey Smirnov
@ 2019-01-28 10:36 ` Lucas Stach
  1 sibling, 0 replies; 3+ messages in thread
From: Lucas Stach @ 2019-01-28 10:36 UTC (permalink / raw)
  To: Fabio Estevam, shawnguo; +Cc: kernel, linux-imx, linux-arm-kernel

Hi Fabio,

Am Samstag, den 26.01.2019, 19:28 -0200 schrieb Fabio Estevam:
> Add support for the three ECSPI ports present on i.MX8MQ.
> 
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 +++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 892063a7c26c..45b9d4a8b0da 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -26,6 +26,9 @@
>  		serial1 = &uart2;
>  		serial2 = &uart3;
>  		serial3 = &uart4;
> +		spi0 = &ecspi1;
> +		spi1 = &ecspi2;
> +		spi2 = &ecspi3;
>  	};
>  
>  	ckil: clock-ckil {
> @@ -381,6 +384,42 @@
>  			#size-cells = <1>;
>  			ranges = <0x30800000 0x30800000 0x400000>;
>  
> +			ecspi1: spi@30820000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
> +				reg = <0x0 0x30820000 0x0 0x10000>;

reg is a single address and size cell in the upstream DT, as all
peripherals are below the 4GB mark, so we just expand the addresses by
using a DT range in the soc node.

Regards,
Lucas

> +				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
> +					 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			ecspi2: spi@30830000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
> +				reg = <0x0 0x30830000 0x0 0x10000>;
> +				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
> +					 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			ecspi3: spi@30840000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
> +				reg = <0x0 0x30840000 0x0 0x10000>;
> +				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
> +					 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
>  			uart1: serial@30860000 {
>  				compatible = "fsl,imx8mq-uart",
>  				             "fsl,imx6q-uart";


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^ permalink raw reply	[flat|nested] 3+ messages in thread
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