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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id u136sm804401oie.38.2019.01.30.08.17.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 30 Jan 2019 08:17:14 -0800 (PST) Date: Wed, 30 Jan 2019 10:17:14 -0600 From: Rob Herring To: Erin Lo Subject: Re: [PATCH v6 5/6] dt-bindings: pinctrl: mt8183: add binding document Message-ID: <20190130161714.GA24352@bogus> References: <1548317240-44682-1-git-send-email-erin.lo@mediatek.com> <1548317240-44682-6-git-send-email-erin.lo@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1548317240-44682-6-git-send-email-erin.lo@mediatek.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190130_081717_150300_A51826CC X-CRM114-Status: GOOD ( 24.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Jason Cooper , srv_heupstream , Marc Zyngier , Greg Kroah-Hartman , mars.cheng@mediatek.com, Stephen Boyd , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-serial@vger.kernel.org, Zhiyong Tao , Matthias Brugger , yingjoe.chen@mediatek.com, Thomas Gleixner , eddie.huang@mediatek.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 24, 2019 at 04:07:19PM +0800, Erin Lo wrote: > From: Zhiyong Tao > > The commit adds mt8183 compatible node in binding document. > > Signed-off-by: Zhiyong Tao > Signed-off-by: Erin Lo > --- > .../devicetree/bindings/pinctrl/pinctrl-mt8183.txt | 115 +++++++++++++++++++++ > 1 file changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > new file mode 100644 > index 0000000..364e673 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8183.txt > @@ -0,0 +1,115 @@ > +* Mediatek MT8183 Pin Controller > + > +The Mediatek's Pin controller is used to control SoC pins. > + > +Required properties: > +- compatible: value should be one of the following. > + "mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl. > +- gpio-controller : Marks the device node as a gpio controller. > +- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO > + binding is used, the amount of cells must be specified as 2. See the below > + mentioned gpio binding representation for description of particular cells. > +- gpio-ranges : gpio valid number range. > +- reg: physicall address base for gpio base registers. There are nine > + physicall address base in mt8183. They are 0x10005000, 0x11F20000, Still have a typo in 'physicall' > + 0x11E80000, 0x11E70000, 0x11E90000, 0x11D30000, 0x11D20000, 0x11C50000, > + 0x11F30000. You don't need to list the address values. Only how many and what each one is. > + > + Eg: <&pio 6 0> > + <[phandle of the gpio controller node] > + [line number within the gpio controller] > + [flags]> > + > + Values for gpio specifier: > + - Line number: is a value between 0 to 202. > + - Flags: bit field of flags, as defined in . > + Only the following flags are supported: > + 0 - GPIO_ACTIVE_HIGH > + 1 - GPIO_ACTIVE_LOW > + > +Optional properties: > +- reg-names: gpio base register names. There are nine gpio base register > + names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", > + "iocfg5", "iocfg6", "iocfg7", "iocfg8". As I said before, these names aren't useful. There's already inheritently an index with 'reg'. Unless some are optional and can be sparsely populated. > +- interrupt-controller: Marks the device node as an interrupt controller > +- #interrupt-cells: Should be two. > +- interrupts : The interrupt outputs from the controller. > + > +Please refer to pinctrl-bindings.txt in this directory for details of the > +common pinctrl bindings used by client devices. > + > +Subnode format > +A pinctrl node should contain at least one subnodes representing the > +pinctrl groups available on the machine. Each subnode will list the > +pins it needs, and how they should be configured, with regard to muxer > +configuration, pullups, drive strength, input enable/disable and input schmitt. > + > + node { > + pinmux = ; > + GENERIC_PINCONFIG; > + }; > + > +Required properties: > +- pinmux: integer array, represents gpio pin number and mux setting. > + Supported pin number and mux varies for different SoCs, and are defined > + as macros in boot/dts/-pinfunc.h directly. > + > +Optional properties: > +- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, > + bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high, > + input-schmitt-enable, input-schmitt-disable and drive-strength are valid. > + > + Some special pins have extra pull up strength, there are R0 and R1 pull-up > + resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11. > + So when config mediatek,pull-up-adv or mediatek,pull-down-adv, > + it support arguments for those special pins. > + > + When config drive-strength, it can support some arguments, such as > + MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. > + > +Examples: > + > +#include "mt8183-pinfunc.h" > + > +... > +{ > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11F20000 0 0x1000>, > + <0 0x11E80000 0 0x1000>, > + <0 0x11E70000 0 0x1000>, > + <0 0x11E90000 0 0x1000>, > + <0 0x11D30000 0 0x1000>, > + <0 0x11D20000 0 0x1000>, > + <0 0x11C50000 0 0x1000>, > + <0 0x11F30000 0 0x1000>; Use lowercase hex. > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; > + #interrupt-cells = <2>; > + > + i2c0_pins_a: i2c0 { > + pins1 { > + pinmux = , > + ; > + mediatek,pull-up-adv = <11>; > + }; > + }; > + > + i2c1_pins_a: i2c1 { > + pins { > + pinmux = , > + ; > + mediatek,pull-down-adv = <10>; > + }; > + }; > + ... > + }; > +}; > -- > 1.9.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel