From: Joseph Lo <josephl@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Joseph Lo <josephl@nvidia.com>
Subject: [PATCH] arm64: dts: tegra210: Add L2 cache topology
Date: Fri, 1 Feb 2019 11:43:47 +0800 [thread overview]
Message-ID: <20190201034347.18470-1-josephl@nvidia.com> (raw)
Add L2 cache topology.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
Notice that,
This patch depends on the series of CPU idle support[1].
And that one depneds on [2].
[1]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=89446
[2]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=84380
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 75534692604c..baf3d45c46e8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1319,6 +1319,7 @@
clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
clock-latency = <300000>;
cpu-idle-states = <&C7>;
+ next-level-cache = <&L2>;
};
cpu@1 {
@@ -1326,6 +1327,7 @@
compatible = "arm,cortex-a57";
reg = <1>;
cpu-idle-states = <&C7>;
+ next-level-cache = <&L2>;
};
cpu@2 {
@@ -1333,6 +1335,7 @@
compatible = "arm,cortex-a57";
reg = <2>;
cpu-idle-states = <&C7>;
+ next-level-cache = <&L2>;
};
cpu@3 {
@@ -1340,6 +1343,7 @@
compatible = "arm,cortex-a57";
reg = <3>;
cpu-idle-states = <&C7>;
+ next-level-cache = <&L2>;
};
idle-states {
@@ -1356,6 +1360,10 @@
status = "disabled";
};
};
+
+ L2: l2-cache {
+ compatible = "cache";
+ };
};
timer {
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2019-02-01 3:44 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 3:43 Joseph Lo [this message]
2019-03-28 16:10 ` [PATCH] arm64: dts: tegra210: Add L2 cache topology Thierry Reding
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190201034347.18470-1-josephl@nvidia.com \
--to=josephl@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-tegra@vger.kernel.org \
--cc=thierry.reding@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).