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From: "Guido Günther" <agx@sigxcpu.org>
To: Sam Ravnborg <sam@ravnborg.org>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>,
	Robert Chiras <robert.chiras@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 2/2] phy: Add driver for mixel dphy
Date: Fri, 1 Feb 2019 09:54:55 +0100	[thread overview]
Message-ID: <20190201085455.GA32742@bogon.m.sigxcpu.org> (raw)
In-Reply-To: <20190125165355.GA3522@ravnborg.org>

Hi Sam,
On Fri, Jan 25, 2019 at 05:53:55PM +0100, Sam Ravnborg wrote:
[..snip..]
> > +struct mixel_dphy_cfg {
> > +	u32 cm;
> > +	u32 cn;
> > +	u32 co;
> > +	unsigned long hs_clk_rate;
> > +	u8 mc_prg_hs_prepare;
> > +	u8 m_prg_hs_prepare;
> > +	u8 mc_prg_hs_zero;
> > +	u8 m_prg_hs_zero;
> > +	u8 mc_prg_hs_trail;
> > +	u8 m_prg_hs_trail;
> > +};
> 
> For the naive reader it would be helpful to spell out the names in a comment.
> As I assume the names comes from the data sheet the short names are OK - but
> let others know the purpose.

These are actual register names so I added comment just saying that.

[..snip..]
> > +static int mixel_dphy_config_from_opts(struct phy *phy,
> > +	       struct phy_configure_opts_mipi_dphy *dphy_opts,
> > +	       struct mixel_dphy_cfg *cfg)
> > +{
> Align extra paratmers below the first parameter using tabs and add necessary
> spaces.

Due to the long phy_configure_opts_mipi_dpy this whole hit the 80 char
limit so I left it like that to make checkpatch happy.

> 
> > +	struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
> > +	unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk);
> > +	int i;
> > +	unsigned long numerator, denominator, frequency;
> > +	unsigned step;
> > +
> > +static int mixel_dphy_ref_power_on(struct phy *phy)
> > +{
> > +	struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
> > +	u32 lock, timeout;
> > +	int ret = 0;
> > +
> > +	mutex_lock(&priv->lock);
> > +	clk_prepare_enable(priv->phy_ref_clk);
> > +
> > +	phy_write(phy, PWR_ON, DPHY_PD_DPHY);
> > +	phy_write(phy, PWR_ON, DPHY_PD_PLL);
> > +
> > +	timeout = 100;
> > +	while (!(lock = phy_read(phy, DPHY_LOCK))) {
> > +		udelay(10);
> > +		if (--timeout == 0) {
> > +			dev_err(&phy->dev, "Could not get DPHY lock!\n");
> > +			mutex_unlock(&priv->lock);
> > +			return -EINVAL;
> > +		}
> USe goto to have a single exit path where you do mutex_unlock()

Using regmap I could drop the lock entirely.

[..snip..]
> > +static const struct mixel_dphy_ops mixel_dphy_ref_ops = {
> > +	.power_on = mixel_dphy_ref_power_on,
> > +	.power_off = mixel_dphy_ref_power_off,
> > +};
> > +
> > +static const struct phy_ops mixel_dphy_ops = {
> > +	.power_on = mixel_dphy_power_on,
> > +	.power_off = mixel_dphy_power_off,
> > +	.configure = mixel_dphy_configure,
> > +	.validate = mixel_dphy_validate,
> > +	.owner = THIS_MODULE,
> > +};
> This is confusing.
> We have struct mixel_dphy_ops => mixel_dphy_ref_ops
> And then struct phy_ops => mixel_dphy_ops
> 
> So reading this there are to uses of mixel_dphy_ops,
> one is a struct, and another is an instance of another type.
> Try to find a niming scheme that is less confusing.

Yeah, that's true. I found in another driver other imx8 variants have
different register offsets so I went for register offsets in devdata
rather than function pointer table which make this ambiguity go away too.
I hope I have tackled all your other comments.

Thanks!
 -- Guido

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  reply	other threads:[~2019-02-01  8:55 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-25 10:14 [PATCH 0/2] RFC: Mixel DPHY support for i.MX8 Guido Günther
2019-01-25 10:14 ` [PATCH 1/2] dt-bindings: phy: Add documentation for mixel dphy Guido Günther
2019-01-25 10:14 ` [PATCH 2/2] phy: Add driver " Guido Günther
2019-01-25 16:53   ` Sam Ravnborg
2019-02-01  8:54     ` Guido Günther [this message]
2019-01-28 15:10   ` Fabio Estevam
2019-01-30  9:15     ` Guido Günther

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