From: Rob Herring <robh@kernel.org>
To: shun-chih.yu@mediatek.com
Cc: devicetree@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
linux-kernel@vger.kernel.org, srv_wsdupstream@mediatek.com,
dmaengine@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Dan Williams <dan.j.williams@intel.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/1] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
Date: Mon, 18 Feb 2019 08:47:19 -0600 [thread overview]
Message-ID: <20190218144719.GA28079@bogus> (raw)
In-Reply-To: <1550130058-16566-2-git-send-email-shun-chih.yu@mediatek.com>
On Thu, Feb 14, 2019 at 03:40:58PM +0800, shun-chih.yu@mediatek.com wrote:
> From: Shun-Chih Yu <shun-chih.yu@mediatek.com>
>
> Document the devicetree bindings for MediaTek Command-Queue DMA controller
> which could be found on MT6765 SoC or other similar Mediatek SoCs.
>
> Change-Id: I9736c8cac9be160358feeab935fabaffc5730519
Drop this.
> Signed-off-by: Shun-Chih Yu <shun-chih.yu@mediatek.com>
> ---
> .../devicetree/bindings/dma/mtk-cqdma.txt | 31 ++++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
> new file mode 100644
> index 0000000..fb12927
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
> @@ -0,0 +1,31 @@
> +MediaTek Command-Queue DMA Controller
> +==================================
> +
> +Required properties:
> +
> +- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
> +- reg: Should contain the base address and length for each channel.
> +- interrupts: Should contain references to the interrupts for each channel.
> +- clocks: Should be the clock specifiers corresponding to the entry in
> + clock-names property.
> +- clock-names: Should contain "cqdma" entries.
> +- dma-channels: The number of DMA channels supported by the controller.
What's the range of valid values?
> +- dma-requests: The number of DMA request supported by the controller.
What's the range of valid values?
> +- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
> + in dmas property of a client device represents the channel
> + number.
> +Example:
> +
> + cqdma: dma-controller@10212000 {
> + compatible = "mediatek,mt6765-cqdma";
> + reg = <0 0x10212000 0 0x1000>;
Should be 2 entries here since there are 2 channels? Or the description
above is wrong.
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_IFR_CQ_DMA>;
> + clock-names = "cqdma";
> + dma-channels = <2>;
> + dma-requests = <32>;
> + #dma-cells = <1>;
> + };
> +
> +DMA clients must use the format described in dma/dma.txt file.
> --
> 1.7.9.5
>
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prev parent reply other threads:[~2019-02-18 14:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-14 7:40 [PATCH] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings shun-chih.yu
2019-02-14 7:40 ` [PATCH 1/1] " shun-chih.yu
2019-02-18 14:47 ` Rob Herring [this message]
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