Re: [PATCH 07/15] mtd: rawnand: Fill memorg during detection

From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Schrempf Frieder <frieder.schrempf@kontron.de>
Cc: Mason Yang <masonccyang@mxic.com.tw>, Vignesh R <vigneshr@ti.com>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>,
	Julien Su <juliensu@mxic.com.tw>,
	Richard Weinberger <richard@nod.at>,
	Boris Brezillon <bbrezillon@kernel.org>,
	Marek Vasut <marek.vasut@gmail.com>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 07/15] mtd: rawnand: Fill memorg during detection
Date: Tue, 26 Feb 2019 14:09:03 +0100	[thread overview]
Message-ID: <20190226140903.7d0f3916@xps13> (raw)
In-Reply-To: <2442d400-d50d-bbe9-4275-cce2241f6609@kontron.de>

Hi Frieder,

Schrempf Frieder <frieder.schrempf@kontron.de> wrote on Sat, 23 Feb
2019 13:00:14 +0000:

> On 21.02.19 10:15, Miquel Raynal wrote:
> > From: Boris Brezillon <bbrezillon@kernel.org>
> > 
> > If we want to use the generic NAND layer, we need to have the memorg
> > struct appropriately filled. Patch the detection code to fill this
> > struct.
> > 
> > Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >   drivers/mtd/nand/raw/denali.c       |  5 +++
> >   drivers/mtd/nand/raw/diskonchip.c   |  4 ++
> >   drivers/mtd/nand/raw/jz4740_nand.c  |  4 ++
> >   drivers/mtd/nand/raw/nand_amd.c     | 11 ++++--
> >   drivers/mtd/nand/raw/nand_base.c    | 60 ++++++++++++++++++++++++++---
> >   drivers/mtd/nand/raw/nand_hynix.c   | 48 +++++++++++++++--------
> >   drivers/mtd/nand/raw/nand_jedec.c   | 22 ++++++++---
> >   drivers/mtd/nand/raw/nand_onfi.c    | 23 ++++++++---
> >   drivers/mtd/nand/raw/nand_samsung.c | 24 ++++++++----
> >   drivers/mtd/nand/raw/nand_toshiba.c |  9 ++++-
> >   drivers/mtd/nand/raw/nandsim.c      |  6 +++
> >   11 files changed, 172 insertions(+), 44 deletions(-)
> >   
> [...]
> > diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
> > index d3092c9a3e21..cb03877c775c 100644
> > --- a/drivers/mtd/nand/raw/nand_base.c
> > +++ b/drivers/mtd/nand/raw/nand_base.c
> > @@ -4530,21 +4530,30 @@ static int nand_get_bits_per_cell(u8 cellinfo)
> >    */
> >   void nand_decode_ext_id(struct nand_chip *chip)
> >   {
> > +	struct nand_memory_organization *memorg;
> >   	struct mtd_info *mtd = nand_to_mtd(chip);
> >   	int extid;
> >   	u8 *id_data = chip->id.data;
> > +
> > +	memorg = nanddev_get_memorg(&chip->base);
> > +
> >   	/* The 3rd id byte holds MLC / multichip data */
> > +	memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
> >   	chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
> >   	/* The 4th id byte is the important one */
> >   	extid = id_data[3];
> >   
> >   	/* Calc pagesize */
> > -	mtd->writesize = 1024 << (extid & 0x03);
> > +	memorg->pagesize = 1024 << (extid & 0x03);
> > +	mtd->writesize = memorg->pagesize;
> >   	extid >>= 2;
> >   	/* Calc oobsize */
> > -	mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
> > +	memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
> > +	mtd->oobsize = memorg->oobsize;
> >   	extid >>= 2;
> >   	/* Calc blocksize. Blocksize is multiples of 64KiB */
> > +	memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /
> > +				       memorg->pagesize;
> >   	mtd->erasesize = (64 * 1024) << (extid & 0x03);
> >   	extid >>= 2;
> >   	/* Get buswidth information */
> > @@ -4561,12 +4570,19 @@ EXPORT_SYMBOL_GPL(nand_decode_ext_id);
> >   static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
> >   {
> >   	struct mtd_info *mtd = nand_to_mtd(chip);
> > +	struct nand_memory_organization *memorg;
> >   
> > +	memorg = nanddev_get_memorg(&chip->base);
> > +
> > +	memorg->pages_per_eraseblock = type->erasesize / type->pagesize;
> >   	mtd->erasesize = type->erasesize;
> > -	mtd->writesize = type->pagesize;
> > -	mtd->oobsize = mtd->writesize / 32;
> > +	memorg->pagesize = type->pagesize;
> > +	mtd->writesize = memorg->pagesize;
> > +	memorg->oobsize = memorg->pagesize / 32;
> > +	mtd->oobsize = memorg->oobsize;
> >   
> >   	/* All legacy ID NAND are small-page, SLC */
> > +	memorg->bits_per_cell = 1;
> >   	chip->bits_per_cell = 1;
> >   }
> >   
> > @@ -4595,13 +4611,21 @@ static bool find_full_id_nand(struct nand_chip *chip,
> >   			      struct nand_flash_dev *type)
> >   {
> >   	struct mtd_info *mtd = nand_to_mtd(chip);
> > +	struct nand_memory_organization *memorg;
> >   	u8 *id_data = chip->id.data;
> >   
> > +	memorg = nanddev_get_memorg(&chip->base);
> > +
> >   	if (!strncmp(type->id, id_data, type->id_len)) {
> > -		mtd->writesize = type->pagesize;
> > +		memorg->pagesize = type->pagesize;
> > +		mtd->writesize = memorg->pagesize;
> > +		memorg->pages_per_eraseblock = type->erasesize /
> > +					       type->erasesize;  
> 
> This should be:
> 		memorg->pages_per_eraseblock = type->erasesize /
> 					       type->pagesize;

Good catch!

I will correct that, and also clean the mixed declarations between
patch 7 and patch 13 you spotted.

Thanks,
Miquèl

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