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Thu, 07 Mar 2019 09:24:34 -0800 (PST) Date: Thu, 7 Mar 2019 22:54:26 +0530 From: Manivannan Sadhasivam To: linux-arm-kernel@lists.infradead.org, linus.walleij@linaro.org Subject: Re: [PATCH 1/2] arm64: dts: bitmain: Add GPIO support for BM1880 SoC Message-ID: <20190307172426.GA9268@Mani-XPS-13-9360> References: <20190226115022.19022-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190226115022.19022-1-manivannan.sadhasivam@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_092436_635603_17F8B4D3 X-CRM114-Status: GOOD ( 14.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kucheria@linaro.org, darren.tsao@bitmain.com, linux-gpio@vger.kernel.org, haitao.suo@bitmain.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 26, 2019 at 05:20:21PM +0530, Manivannan Sadhasivam wrote: > Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO > controller IP. IP exposes 3 GPIO controllers with a total of 72 pins. > Applied for v5.2 with Linus's Reviewed-by tag. Thanks, Mani > Signed-off-by: Manivannan Sadhasivam > --- > arch/arm64/boot/dts/bitmain/bm1880.dtsi | 54 +++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi > index 55a4769e0de2..e4da4ec6a5ee 100644 > --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi > +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi > @@ -80,6 +80,60 @@ > #interrupt-cells = <3>; > }; > > + gpio0: gpio@50027000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dw-apb-gpio"; > + reg = <0x0 0x50027000 0x0 0x400>; > + > + porta: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = ; > + }; > + }; > + > + gpio1: gpio@50027400 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dw-apb-gpio"; > + reg = <0x0 0x50027400 0x0 0x400>; > + > + portb: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <32>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = ; > + }; > + }; > + > + gpio2: gpio@50027800 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "snps,dw-apb-gpio"; > + reg = <0x0 0x50027800 0x0 0x400>; > + > + portc: gpio-controller@0 { > + compatible = "snps,dw-apb-gpio-port"; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <8>; > + reg = <0>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = ; > + }; > + }; > + > uart0: serial@58018000 { > compatible = "snps,dw-apb-uart"; > reg = <0x0 0x58018000 0x0 0x2000>; > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel