From: Sudeep Holla <sudeep.holla@arm.com>
To: Benjamin Gaignard <benjamin.gaignard@st.com>
Cc: robh@kernel.org, loic.pallardy@st.com, arnd@arndb.de,
gregkh@linuxfoundation.org, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, broonie@kernel.org,
linux-imx@nxp.com, benjamin.gaignard@linaro.org,
fabio.estevam@nxp.com, shawnguo@kernel.org,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org
Subject: Re: [RESEND PATCH 0/7] Introduce bus domains controller framework
Date: Mon, 18 Mar 2019 10:43:43 +0000 [thread overview]
Message-ID: <20190318104343.GA15574@e107155-lin> (raw)
In-Reply-To: <20190318100605.29120-1-benjamin.gaignard@st.com>
On Mon, Mar 18, 2019 at 11:05:58AM +0100, Benjamin Gaignard wrote:
> Bus domains controllers allow to divided system on chip into multiple domains
> that can be used to select by who hardware blocks could be accessed.
> A domain could be a cluster of CPUs (or coprocessors), a range of addresses or
> a group of hardware blocks.
>
> Framework architecture is inspirated by pinctrl framework:
> - a default configuration could be applied before bind the driver
> - configurations could be apllied dynamically by drivers
> - device node provides the bus domains configurations
>
> An example of bus domains controller is STM32 ETZPC hardware block
> which got 3 domains:
> - secure: hardware blocks are only accessible by software running on trust
> zone.
> - non-secure: hardware blocks are accessible by non-secure software (i.e.
> linux kernel).
> - coprocessor: hardware blocks are only accessible by the corpocessor.
> Up to 94 hardware blocks of the soc could be managed by ETZPC and
> assigned to one of the three domains.
>
You fail to explain why do we need this in non-secure Linux ?
You need to have solid reasons as why this can't be done in secure
firmware. And yes I mean even on arm32. On platforms with such hardware
capabilities you will need some secure firmware to be running and these
things can be done there. I don't want this enabled for ARM64 at all,
firmware *has to deal* with this.
--
Regards,
Sudeep
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next prev parent reply other threads:[~2019-03-18 10:44 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-18 10:05 [RESEND PATCH 0/7] Introduce bus domains controller framework Benjamin Gaignard
2019-03-18 10:05 ` [RESEND PATCH 1/7] devicetree: bindings: Document domains controller bindings Benjamin Gaignard
2019-04-29 8:49 ` Benjamin GAIGNARD
2019-03-18 10:06 ` [RESEND PATCH 2/7] domainsctrl: Introduce domains controller framework Benjamin Gaignard
2019-03-18 10:06 ` [RESEND PATCH 3/7] base: Add calls to domains controller Benjamin Gaignard
2019-03-18 10:06 ` [RESEND PATCH 4/7] devicetree: bindings: domainsctrl: Add STM32 ETZPC bindings Benjamin Gaignard
2019-03-18 10:06 ` [RESEND PATCH 5/7] bus: domainsctrl: Add driver for STM32 ETZPC controller Benjamin Gaignard
2019-03-18 10:06 ` [RESEND PATCH 6/7] ARM: dts: stm32: Add domainsctrl node for stm32mp157 SoC Benjamin Gaignard
2019-03-18 10:06 ` [RESEND PATCH 7/7] ARM: dts: stm32: enable domains controller node on stm32mp157c-ed1 Benjamin Gaignard
2019-03-18 10:43 ` Sudeep Holla [this message]
2019-03-18 11:05 ` [RESEND PATCH 0/7] Introduce bus domains controller framework Benjamin Gaignard
2019-04-19 12:36 ` Benjamin Gaignard
2019-04-23 7:41 ` Enrico Weigelt, metux IT consult
2019-04-23 13:21 ` Sudeep Holla
2019-04-23 13:33 ` Benjamin GAIGNARD
2019-04-23 13:55 ` Sudeep Holla
2019-04-23 14:17 ` Benjamin GAIGNARD
2019-04-25 18:01 ` Mark Brown
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