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Thu, 21 Mar 2019 05:00:24 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 21 Mar 2019 05:00:23 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Thu, 21 Mar 2019 05:00:23 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2LA0KO6014903; Thu, 21 Mar 2019 05:00:20 -0500 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Bjorn Helgaas , Gustavo Pimentel , Marc Zyngier Subject: [PATCH v5 0/8] PCI: DWC/Keystone: MSI configuration cleanup Date: Thu, 21 Mar 2019 15:29:19 +0530 Message-ID: <20190321095927.7058-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190321_030036_399371_B3DA57B1 X-CRM114-Status: GOOD ( 14.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jingoo Han , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Kishon Vijay Abraham I Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series tries to address the comments discussed in [1] w.r.t removing Keystone specific callbacks defined in dw_pcie_host_ops. This series also tries to cleanup the Keystone interrupt handling part. Changes from v4: *) Removed legacy interrupt cleanup patch which uses hierarchy IRQ domain since TI platform uses edge interrupt for legacy interrupt. This will be deferred till I get more details from HW team. Changes from v3: *) Uses hierarchy IRQ domain for legacy interrupts since there is 1:1 mapping between legacy interrupt and GIC IRQ. (MSI still depends on the order of IRQs populated in dt). Changes from v2: *) Removed patch that modifies ks_pcie_legacy_irq_handler() to check the IRQ_STATUS of INTA/B/C/D. Lorenzo's comment to create a matrix LinuxIRQ x INTx will be added in AM654x PCIe support series *) ks_pcie_legacy_irq_handler() is made to use hwirq to get IRQ offset instead of virq. *) default msi_irq_chip is assigned in dw_pcie_host_init() once keystone assigns its msi_irq_chip *) Fixed other minor comments from Lorenzo and Bjorn Changes from v1: *) Removed "PCI: keystone: Use "dummy_irq_chip" instead of new irqchip for legacy interrupt handling" from the patch series. It should be handled differently. *) Added Gustavo's ACKed by and fixed a commit message. [1] -> https://patchwork.kernel.org/patch/10681587/ Kishon Vijay Abraham I (8): PCI: keystone: Cleanup interrupt related macros PCI: keystone: Add separate functions for configuring MSI and legacy interrupt PCI: keystone: Use hwirq to get the MSI IRQ number offset PCI: keystone: Cleanup ks_pcie_msi_irq_handler PCI: dwc: Add support to use non default msi_irq_chip PCI: keystone: Use Keystone specific msi_irq_chip PCI: dwc: Remove Keystone specific dw_pcie_host_ops PCI: dwc: Do not write to MSI control registers if the platform doesn't use it drivers/pci/controller/dwc/pci-keystone.c | 365 ++++++++++-------- .../pci/controller/dwc/pcie-designware-host.c | 78 ++-- drivers/pci/controller/dwc/pcie-designware.h | 6 +- 3 files changed, 233 insertions(+), 216 deletions(-) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel