* [PATCH v4 0/3] Add support for Eckelmann ci4x10
@ 2019-03-20 9:12 Uwe Kleine-König
2019-03-20 9:12 ` [PATCH v4 1/3] dt-bindings: arm: fsl: Add devicetree binding " Uwe Kleine-König
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Uwe Kleine-König @ 2019-03-20 9:12 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
Hello,
compared to v3 there are only minor changes in this v4.
- Address Feedback by Shawn (memory@10000000 instead of memory, status
at end of property list)
- Add Fabio's Reviewed-by tag.
- Write "ci4x10" consistently in lower case
- add DT people to To of the first patch as this needs their ack.
Uwe Kleine-König (3):
dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10
ARM: dts: Add devicetree for Eckelmann ci4x10
ARM: imx_v6_v7_defconfig: Enable SIOX bus
.../devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 381 ++++++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 3 +
4 files changed, 386 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
--
2.20.1
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/3] dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10
2019-03-20 9:12 [PATCH v4 0/3] Add support for Eckelmann ci4x10 Uwe Kleine-König
@ 2019-03-20 9:12 ` Uwe Kleine-König
2019-03-24 21:21 ` Rob Herring
2019-03-20 9:12 ` [PATCH v4 2/3] ARM: dts: Add devicetree " Uwe Kleine-König
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Uwe Kleine-König @ 2019-03-20 9:12 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, Mark Rutland
Cc: devicetree, Gavin Schenk, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, linux-arm-kernel
Add devicetree binding for Eckelmann's ci4x10 board which is powered by
an i.MX6DL SoC.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 7e2cd6ad26bd..ae32a2e9e232 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -90,6 +90,7 @@ properties:
- description: i.MX6DL based Boards
items:
- enum:
+ - eckelmann,imx6dl-ci4x10
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
- technologic,imx6dl-ts4900
--
2.20.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 2/3] ARM: dts: Add devicetree for Eckelmann ci4x10
2019-03-20 9:12 [PATCH v4 0/3] Add support for Eckelmann ci4x10 Uwe Kleine-König
2019-03-20 9:12 ` [PATCH v4 1/3] dt-bindings: arm: fsl: Add devicetree binding " Uwe Kleine-König
@ 2019-03-20 9:12 ` Uwe Kleine-König
2019-03-20 9:12 ` [PATCH v4 3/3] ARM: imx_v6_v7_defconfig: Enable SIOX bus Uwe Kleine-König
2019-03-26 8:30 ` [PATCH v4 0/3] Add support for Eckelmann ci4x10 Shawn Guo
3 siblings, 0 replies; 6+ messages in thread
From: Uwe Kleine-König @ 2019-03-20 9:12 UTC (permalink / raw)
To: Shawn Guo
Cc: Gavin Schenk, NXP Linux Team, Pengutronix Kernel Team,
Fabio Estevam, Fabio Estevam, linux-arm-kernel
This is one of two boards that make use of the recently introduced SIOX
bus. Apart from the devices described in the dts it features a display
with touch that I didn't include here because it needs some non-mainline
change to operate correctly.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 381 ++++++++++++++++++
2 files changed, 382 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4f5aeaf3298..3332dbf2a979 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -400,6 +400,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dfi-fs700-m60.dtb \
+ imx6dl-eckelmann-ci4x10.dtb \
imx6dl-emcon-avari.dtb \
imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
new file mode 100644
index 000000000000..9eb2b73951b2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Eckelmann AG.
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx6dl.dtsi"
+
+/ {
+ model = "Eckelmann CI 4X10 Board";
+ compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
+
+ rmii_clk: clock-rmii {
+ /* This clock is provided by the phy (KSZ8091RNB) */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ siox {
+ compatible = "eckelmann,siox-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_siox>;
+ din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
+ dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+ dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
+ dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "everspin,mr25h256";
+ reg = <0>;
+ spi-max-frequency = <15000000>;
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ tpm@0 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+};
+
+&gpio2 {
+ gpio-line-names = "buzzer", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio4 {
+ gpio-line-names = "", "", "", "", "", "", "", "in2",
+ "prio2", "prio1", "aux", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&gpio6 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "in1",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ temperature-sensor@49 {
+ compatible = "ad,ad7414";
+ reg = <0x49>;
+ };
+
+ rtc@51 {
+ compatible = "nxp,pcf2127";
+ reg = <0x51>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hog {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */
+
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0
+ MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0
+ MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0
+ MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0
+ MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ /* without SION i2c doesn't detect bus busy */
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018
+ >;
+ };
+
+ pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0
+ >;
+ };
+
+ pinctrl_siox: sioxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */
+ >;
+ };
+
+ pinctrl_uart1_dte: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */
+ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */
+ >;
+ };
+
+ pinctrl_uart2_dte: uart2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010
+ MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010
+ MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */
+ >;
+ };
+
+ pinctrl_uart3_dce: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010
+ MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010
+ >;
+ };
+
+ pinctrl_uart4_dce: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010
+ >;
+ };
+
+ pinctrl_uart5_dce: uart5grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010
+ MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */
+ >;
+ };
+
+ pinctrl_usbh1: usbh1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059
+ >;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ phy-handle = <&phy>;
+ clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_dte>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+ dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte>;
+ uart-has-rtscts;
+ fsl,dte-mode;
+ dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_dce>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4_dce>;
+ rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5_dce>;
+ rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbh1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1>;
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
--
2.20.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 3/3] ARM: imx_v6_v7_defconfig: Enable SIOX bus
2019-03-20 9:12 [PATCH v4 0/3] Add support for Eckelmann ci4x10 Uwe Kleine-König
2019-03-20 9:12 ` [PATCH v4 1/3] dt-bindings: arm: fsl: Add devicetree binding " Uwe Kleine-König
2019-03-20 9:12 ` [PATCH v4 2/3] ARM: dts: Add devicetree " Uwe Kleine-König
@ 2019-03-20 9:12 ` Uwe Kleine-König
2019-03-26 8:30 ` [PATCH v4 0/3] Add support for Eckelmann ci4x10 Shawn Guo
3 siblings, 0 replies; 6+ messages in thread
From: Uwe Kleine-König @ 2019-03-20 9:12 UTC (permalink / raw)
To: Shawn Guo
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
Now that there is a board making use of this bus is available
enable the siox code to increase compile coverage.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
arch/arm/configs/imx_v6_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 5586a5074a96..05680adc355e 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -211,6 +211,7 @@ CONFIG_SPI_GPIO=y
CONFIG_SPI_IMX=y
CONFIG_SPI_FSL_DSPI=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_SIOX=m
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_MC9S08DZ60=y
CONFIG_GPIO_PCA953X=y
@@ -404,6 +405,8 @@ CONFIG_NVMEM_VF610_OCOTP=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_MUX_MMIO=y
+CONFIG_SIOX=m
+CONFIG_SIOX_BUS_GPIO=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
--
2.20.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/3] dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10
2019-03-20 9:12 ` [PATCH v4 1/3] dt-bindings: arm: fsl: Add devicetree binding " Uwe Kleine-König
@ 2019-03-24 21:21 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2019-03-24 21:21 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Mark Rutland, devicetree, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Wed, Mar 20, 2019 at 4:13 AM Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
>
> Add devicetree binding for Eckelmann's ci4x10 board which is powered by
> an i.MX6DL SoC.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 0/3] Add support for Eckelmann ci4x10
2019-03-20 9:12 [PATCH v4 0/3] Add support for Eckelmann ci4x10 Uwe Kleine-König
` (2 preceding siblings ...)
2019-03-20 9:12 ` [PATCH v4 3/3] ARM: imx_v6_v7_defconfig: Enable SIOX bus Uwe Kleine-König
@ 2019-03-26 8:30 ` Shawn Guo
3 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2019-03-26 8:30 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Fabio Estevam, Gavin Schenk, NXP Linux Team,
Pengutronix Kernel Team, linux-arm-kernel
On Wed, Mar 20, 2019 at 10:12:51AM +0100, Uwe Kleine-König wrote:
> Hello,
>
> compared to v3 there are only minor changes in this v4.
>
> - Address Feedback by Shawn (memory@10000000 instead of memory, status
> at end of property list)
> - Add Fabio's Reviewed-by tag.
> - Write "ci4x10" consistently in lower case
> - add DT people to To of the first patch as this needs their ack.
>
> Uwe Kleine-König (3):
> dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10
> ARM: dts: Add devicetree for Eckelmann ci4x10
> ARM: imx_v6_v7_defconfig: Enable SIOX bus
Applied all, thanks.
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^ permalink raw reply [flat|nested] 6+ messages in thread
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-- links below jump to the message on this page --
2019-03-20 9:12 [PATCH v4 0/3] Add support for Eckelmann ci4x10 Uwe Kleine-König
2019-03-20 9:12 ` [PATCH v4 1/3] dt-bindings: arm: fsl: Add devicetree binding " Uwe Kleine-König
2019-03-24 21:21 ` Rob Herring
2019-03-20 9:12 ` [PATCH v4 2/3] ARM: dts: Add devicetree " Uwe Kleine-König
2019-03-20 9:12 ` [PATCH v4 3/3] ARM: imx_v6_v7_defconfig: Enable SIOX bus Uwe Kleine-König
2019-03-26 8:30 ` [PATCH v4 0/3] Add support for Eckelmann ci4x10 Shawn Guo
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