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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id q11sm1901913pgs.94.2019.03.26.10.55.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Mar 2019 10:55:27 -0700 (PDT) Date: Tue, 26 Mar 2019 11:55:25 -0600 From: Mathieu Poirier To: Suzuki K Poulose Subject: Re: [PATCH v2 13/16] coresight: tmc-etr: Allow events to use the same ETR buffer Message-ID: <20190326175525.GA17902@xps15> References: <20190325215632.17013-1-mathieu.poirier@linaro.org> <20190325215632.17013-14-mathieu.poirier@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190326_105530_148169_D453CE7B X-CRM114-Status: GOOD ( 21.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexander.shishkin@linux.intel.com, coresight@lists.linaro.org, peterz@infradead.org, Mike.Leach@arm.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 26, 2019 at 04:18:35PM +0000, Suzuki K Poulose wrote: > On 03/25/2019 09:56 PM, Mathieu Poirier wrote: > > This patch uses the pid of the process being traced to aggregate traces > > coming from different processors in the same sink, something that is > > required when collecting traces in CPU-wide mode when the CoreSight HW > > enacts a N:1 source/sink topology. > > > > Signed-off-by: Mathieu Poirier > > --- > > .../hwtracing/coresight/coresight-tmc-etr.c | 71 +++++++++++++++++-- > > 1 file changed, 65 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > > index 7254fafdf1c2..cbabf88bd51d 100644 > > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > > @@ -8,6 +8,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -41,6 +42,9 @@ struct etr_perf_buffer { > > void **pages; > > }; > > +static DEFINE_IDR(session_idr); > > +static DEFINE_MUTEX(session_idr_lock); > > Please correct me if I am wrong here. What we now do with this series is > > - One event per CPU and thus one ETR perf buf per CPU. > - One *ETR buf* per PID, from the IDR hash list. > > However, if we have 1:1 situation, we will have : > > N (say 2 ETRs), but one *ETR buf* as they all share the same PID, implying > multiple multiple ETRs will try to use the same etr buf, > which could corrupt the trace data ? Instead, what we need in that > situation is : > > One ETR buf perf PID+ETR device. i.e, etr_bufs must be per ETR. > So should the IDR be specific to an ETR ? > > Or do we not support a session with multiple ETRs involved (1:1) ? At this time 1:1 topologies are not supported and a fair amount of work will go in doing so. When I started working on this serie my thought was that because of said amount of work there is no point thinking about 1:1, and that we can deal with it when we get there. But taking a step back and having dealt with the harder (concurrency) problems inherent to CPU-wide scenarios, it would be trivial to make the code 1:1 ready and it will be one less thing to worry about down the road. That being said and answering your question above, I think we need and IDR per ETR (in the drvdata) to avoid contention issues on systems with several ETRs. Thanks for bringing this back to my attention. Mathieu > > Cheers > Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel