From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64033C43381 for ; Fri, 29 Mar 2019 18:53:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 284472184D for ; Fri, 29 Mar 2019 18:53:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="YVFJBXQz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 284472184D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=px+AQQMOeDsacj40L+3c2UbTXvrceE2gBjRNfRB6Wnw=; b=YVFJBXQzGMoWiN yR2o4kgSxxZOl6LEAs1f+XY3bKa+KHi5MDcrNRH8eM0LEFo5KIZYKhgv98rCjrtctKtJSvi9eyuUl gHtY6Gy2fiCKGa6Pk8/qKc8YlHh8YD/c7zsY9EssGXtTDC4ikrajtgsIZG2rks8WW0XhC/OuxKFuz eEzXuqbDCieH87s4zyT9yLYxK+7DzA5aWk5blXCDpwvDNVnEaxXahaKKkPbOTMSSzBLcKK7Nkk32w jeDsXJreKjLB8wj2+oASe4Va6v0qkfBsIO9MCJCT+WfDBGOfKmJXXGIUNhyP2NL3NmdXHlZpy8PqJ jHCBto103Qa9lxMft6Uw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h9wcj-0006t6-Ed; Fri, 29 Mar 2019 18:53:05 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h9wcg-0006sT-F4 for linux-arm-kernel@lists.infradead.org; Fri, 29 Mar 2019 18:53:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CC5B2A78; Fri, 29 Mar 2019 11:53:01 -0700 (PDT) Received: from arrakis.emea.arm.com (arrakis.cambridge.arm.com [10.1.196.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 747233F59C; Fri, 29 Mar 2019 11:53:00 -0700 (PDT) Date: Fri, 29 Mar 2019 18:52:57 +0000 From: Catalin Marinas To: Zhangshaokun Subject: Re: [PATCH] arm64: cache: Update cache_line_size for HiSilicon certain platform Message-ID: <20190329185257.GD48010@arrakis.emea.arm.com> References: <1553581690-24753-1-git-send-email-zhangshaokun@hisilicon.com> <20190326145510.GB33308@arrakis.emea.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190329_115302_511425_49651956 X-CRM114-Status: GOOD ( 24.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , John Garry , Will Deacon , Zhenfa Qiu , Hanjun Guo , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 27, 2019 at 03:16:34PM +0800, Zhangshaokun wrote: > On 2019/3/26 22:55, Catalin Marinas wrote: > > On Tue, Mar 26, 2019 at 02:28:10PM +0800, Shaokun Zhang wrote: > >> For HiSilicon's certain platform, like Kunpeng920 server SoC, it uses the > >> tsv110 CPUs whose L1 cache line size is 64-Byte, while the cache line size > >> of L3C is 128-Byte. > >> cache_line_size is used mostly for IO device drivers, so we shall correct > >> the right value and the device drivers can match it accurately to get good > >> performance. [...] > > What's the CTR_EL0.CWG value on your SoC? > > It's 4'b0100 and cache line size is 64-byte. > > >> When test mlx5 with Kunpeng920 SoC, ib_send_bw is run under the condition > >> that the length of the packet is 4-Byte and only one queue and cpu core: > >> Without this patch: 1.67 Mpps > >> with this patch : 2.40 Mpps > > > > This needs a better explanation. How does cache_line_size() affect the > > 4-byte packet? Does it send more packets at once? > > > > I've seen in the mlx5 code assumptions about cache_line_size() being > > 128. It looks to me more like some driver hand-tuning for specific > > system configuration. Can the driver be changed to be more generic > > I'm not sure that mlx5 may implement some actions for different cache line > size from different arch or platforms, so the driver needs to read the > right cache_line_size. We need to better understand why the performance hit but at a quick grep for "128" in the mlx5 code, I can see different code paths executed when cache_line_size() returned 128 (saved in cqe_size). IOW, presuming you can somehow disable the L3C, do you still see the same performance difference? > Originally, I thought this interface was used mainly for IO drivers and no > harm to any other places. Looking through the slab code, cache_line_size() is used when SLAB_HWCACHE_ALIGN is passed and IIUC this is for performance reasons rather than I/O (the DMA alignment is given by ARCH_DMA_MINALIGN which is 128 on arm64). Anyway, if the performance drop is indeed caused by more L3C cacheline bouncing, we can look at fixing cache_line_size() for your CPU to return 128 but I'd like it done using the cpufeature/errata framework. We have an arm64_ftr_reg_ctrel0.sys_val that we could update to report a 128 byte cacheline and read this in cache_line_size() but I think this may cause user accesses to CTR_EL0 to trap into the kernel to be emulated. This may cause more performance issues for the user than just misreporting the CWG. Alternatively, we store the cache_line_size in a variable and return it. Cc'ing Suzuki for comments on cpu errata approach. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel