From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Jernej Skrabec <jernej.skrabec@siol.net>
Cc: sboyd@kernel.org, mturquette@baylibre.com,
linux-kernel@vger.kernel.org, wens@csie.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/3] clk: sunxi-ng: h6: Preset hdmi-cec clock parent
Date: Wed, 3 Apr 2019 09:54:19 +0200 [thread overview]
Message-ID: <20190403075419.h2vvfiyzvq6xa2zs@flea> (raw)
In-Reply-To: <20190402210623.14988-3-jernej.skrabec@siol.net>
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On Tue, Apr 02, 2019 at 11:06:22PM +0200, Jernej Skrabec wrote:
> H6 manual and BSP clock driver both states that hdmi-cec clock has two
> possible parents, osc32k and pll-periph0-2x with 36621 predivider.
> Because pll-periph0-2x is always 1.2 GHz, both parents give same
> hdmi-cec rate - 32768 Hz, which is exactly the rate needed for HDMI CEC
> controller to operate correctly.
>
> However, for some reason, HDMI CEC controller doesn't work if default
> parent (osc32k) is used. BSP HDMI driver also always use pll-periph0-2x
> as hdmi-cec clock parent.
>
> In order to solve the issue, preset hdmi-cec clock parent to
> pll-periph0-2x.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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next prev parent reply other threads:[~2019-04-03 7:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-02 21:06 [PATCH 0/3] clk: sunxi-ng: H6 related clock fixes Jernej Skrabec
2019-04-02 21:06 ` [PATCH 1/3] clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0) Jernej Skrabec
2019-04-03 7:52 ` Maxime Ripard
2019-04-02 21:06 ` [PATCH 2/3] clk: sunxi-ng: h6: Preset hdmi-cec clock parent Jernej Skrabec
2019-04-03 7:54 ` Maxime Ripard [this message]
2019-04-02 21:06 ` [PATCH 3/3] clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate Jernej Skrabec
2019-04-03 7:54 ` Maxime Ripard
2019-04-03 13:22 ` Chen-Yu Tsai
2019-04-03 14:42 ` Jernej Škrabec
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