From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D654C10F06 for ; Wed, 3 Apr 2019 13:54:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B510206C0 for ; Wed, 3 Apr 2019 13:54:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FKISdmf3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5B510206C0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=f8p6xmIXgwxrWaxyQ2qkhtcnwMwBG3JmHDuqAXHI5Vg=; b=FKISdmf3/z2uc/ +R5XbcSDx4XTrRKGvdj5VM2VzRhKMrgTbjzmu9KkBEXrZiLThRVHRh0zOZ1e2Fq/Epk+h5d/hsCuw 74LDqZ5kH9Y7ftnuZNtBj+NRvlO2uT3tTz5nGKa69flOESPotEun1HBkZA0iduSwTHVB7vys6qeJ0 pDkdN6p6aI9hWoWOAEbQY5E/3EBxxxNr1PkCZIkJbq/fTYkI8nVNkPluhljN4hniGF+UzpvntCmvT WLZYAzvYYkKrNCR//8flAtsN/fy8iOPC2GDh4EvmwxsYrrdXchR90+w3uVEQB+vlAPTXdkWKQ9yRY 2aTKxln661H3pJzgFBVg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBgLG-0000HQ-Eq; Wed, 03 Apr 2019 13:54:14 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBgLD-0000H7-Cn for linux-arm-kernel@lists.infradead.org; Wed, 03 Apr 2019 13:54:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6F0ACA78; Wed, 3 Apr 2019 06:54:10 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 371A43F557; Wed, 3 Apr 2019 06:54:08 -0700 (PDT) Date: Wed, 3 Apr 2019 14:54:05 +0100 From: Will Deacon To: Julien Thierry Subject: Re: [PATCH] arm64: perf: Do not write event type for cycle counter Message-ID: <20190403135405.GB16611@fuggles.cambridge.arm.com> References: <1553766545-27692-1-git-send-email-julien.thierry@arm.com> <20190401080217.r27dgjc43xa5ruzr@blommer> <399b05e9-e309-d5c5-4d41-a672eb4c5d5c@arm.com> <20190403031058.ouek6ecs2xy4dyct@blommer> <2e42ec1f-cc16-d33b-5419-4407c1075d6a@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <2e42ec1f-cc16-d33b-5419-4407c1075d6a@arm.com> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190403_065411_441816_25C3D3F2 X-CRM114-Status: GOOD ( 19.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Peter Zijlstra , Catalin Marinas , Jiri Olsa , Arnaldo Carvalho de Melo , Alexander Shishkin , Ingo Molnar , huawei.libin@huawei.com, guohanjun@huawei.com, Namhyung Kim , liwei391@huawei.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 03, 2019 at 08:26:20AM +0100, Julien Thierry wrote: > On 03/04/2019 04:10, Mark Rutland wrote: > > On Tue, Apr 02, 2019 at 04:42:58PM +0100, Julien Thierry wrote: > >> On 01/04/2019 09:02, Mark Rutland wrote: > >>> On Thu, Mar 28, 2019 at 09:49:05AM +0000, Julien Thierry wrote: > >> Now, I'm thinking what we need is to use a different mask than > >> EVTYPE_MASK (one that excludes the event bits) when setting > >> PMCCFILTR_EL0, but still do that when enabling an event using the cycle > >> counter. > >> > >> Does that approach sound correct? Or am I missing something that would > >> allow us to only set that upon reset? > > > > That sounds right to me! > > > > It would perhaps be nicer if we could configure event->hwc.config_base to be > > the raw register value in all cases, but it looks like that's going to be more > > painful than special-casing the cycle counter here. > > > > Right, I'm gonna need to special case the cycle counter to adapt the > event type writing to this patch[1]. But since this is not as > critical/beneficial as I initially thought, I'll just incorporate the > special-casing to the PMU interrupt as NMI series. I'm confused as to what we're actually fixing here. PMCCFILTR_EL0 and PMEVTYPER_EL0 have the same layout, modulo some RES0 bits, so the existing code should work fine afaict. What's the problem? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel