From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0723C4360F for ; Wed, 3 Apr 2019 17:19:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B1245205C9 for ; Wed, 3 Apr 2019 17:19:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Nb3zKOPg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B1245205C9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Jy41bT1mSg6BtBzQb//GLAYJoncAFKF9LWPwcfzgjD0=; b=Nb3zKOPgDtYQhU qNRKdzEiWZ+bUrc3q1Ny/cWlHGbk6K0gUVN19zJi2fnNERlHZCw/FCWdgKg7np8Y6khmS9SX3CD4R lMywPFWdteokouLM6GObBon+qbANuFZRKJIjQOeCuw8IEgSi4keGut0a/S9wCyG2rPcenztTMAf4f fX0ibgBw6PfqZHxFUSeN+/xKEc1CR7holrDrpCfBzFZYxUB2GZOQqnJ5IRrvyLrIEMbScqY3/YgYM OF6olYLWCkXJoj3qcR45wIs5HaVHx6Lt7Z2nyzGeKCRrp/zNevsOQLncDpU+bxmcVuLsdBLGcT8Q0 qwuf//z8pt8hy6IjvIxg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBjXb-0002PS-Nn; Wed, 03 Apr 2019 17:19:11 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBjXY-0002Ov-84 for linux-arm-kernel@lists.infradead.org; Wed, 03 Apr 2019 17:19:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DCDC680D; Wed, 3 Apr 2019 10:19:07 -0700 (PDT) Received: from red-moon (red-moon.cambridge.arm.com [10.1.197.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3EE503F68F; Wed, 3 Apr 2019 10:19:06 -0700 (PDT) Date: Wed, 3 Apr 2019 18:19:03 +0100 From: Lorenzo Pieralisi To: Kishon Vijay Abraham I Subject: Re: [PATCH v5 8/8] PCI: dwc: Do not write to MSI control registers if the platform doesn't use it Message-ID: <20190403171902.GB3783@red-moon> References: <20190321095927.7058-1-kishon@ti.com> <20190321095927.7058-9-kishon@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190321095927.7058-9-kishon@ti.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190403_101908_293952_B09C2F1F X-CRM114-Status: GOOD ( 20.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Gustavo Pimentel , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Murali Karicheri , Jingoo Han , Bjorn Helgaas , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 21, 2019 at 03:29:27PM +0530, Kishon Vijay Abraham I wrote: > Platforms which populate msi_host_init, has it's own MSI controller > logic. Writing to MSI control registers on platforms which doesn't use > Designware's MSI controller logic might have side effects. To > be safe, do not write to MSI control registers if the platform uses > it's own MSI controller logic instead of Designware's MSI controller > logic. > > Signed-off-by: Kishon Vijay Abraham I > --- > .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- > 1 file changed, 13 insertions(+), 11 deletions(-) This patch is needed regardless of the rest of the series, correct ? A.k.a. it is fixing an issue already in the mainline. Just to make sure we are not _introducing_ a bisection issue with this series up to this patch, in which case I will squash this patch into one of the previous ones, please let me know. Thanks, Lorenzo > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 498422397609..7e0ff7d428a9 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -626,17 +626,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > dw_pcie_setup(pci); > > - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > - > - /* Initialize IRQ Status array */ > - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > - pp->irq_mask[ctrl] = ~0; > - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + > - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > - 4, pp->irq_mask[ctrl]); > - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + > - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > - 4, ~0); > + if (!pp->ops->msi_host_init) { > + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > + > + /* Initialize IRQ Status array */ > + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > + pp->irq_mask[ctrl] = ~0; > + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + > + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > + 4, pp->irq_mask[ctrl]); > + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + > + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > + 4, ~0); > + } > } > > /* Setup RC BARs */ > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel