From: Catalin Marinas <catalin.marinas@arm.com>
To: Zhangshaokun <zhangshaokun@hisilicon.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>,
Suzuki K Poulose <Suzuki.Poulose@arm.com>,
John Garry <john.garry@huawei.com>,
Will Deacon <will.deacon@arm.com>,
Zhenfa Qiu <qiuzhenfa@hisilicon.com>,
Hanjun Guo <guohanjun@huawei.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: cache: Update cache_line_size for HiSilicon certain platform
Date: Thu, 4 Apr 2019 11:27:56 +0100 [thread overview]
Message-ID: <20190404102756.GC43584@arrakis.emea.arm.com> (raw)
In-Reply-To: <c1cecba6-22e7-369a-dd9b-51018ac9cc08@hisilicon.com>
On Tue, Apr 02, 2019 at 03:51:33PM +0800, Zhangshaokun wrote:
> One more question about CWG, if cache line size of L1$ and L2$ on A76 is
> 64-byte and it is used on our platform (L3C cache line is 128-byte), Shall
> CWG is 4b'0100(64-byte) or 4'b0101(128-byte)?
What does /sys/devices/system/cpu/cpu0/cache/index3/coherency_line_size
say on your CPU? This would be information provided by firmware.
Since cache_line_size() in Linux seems to be used for performance rather
than DMA coherency (ARCH_DMA_MINALIGN is the one ensuring this), there
may be a use-case for setting it based on the cache topology description
in ACPI (PPTT) or DT (see drivers/base/cacheinfo.c; also cc'ing Sudeep
since he contributed the cacheinfo code).
But before we change anything in the arch code regarding
cache_line_size(), we need a better understanding of why 128-byte makes
a significant difference (does 256 make it even better?).
--
Catalin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-04-04 10:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-26 6:28 [PATCH] arm64: cache: Update cache_line_size for HiSilicon certain platform Shaokun Zhang
2019-03-26 14:55 ` Catalin Marinas
2019-03-27 7:16 ` Zhangshaokun
2019-03-29 18:52 ` Catalin Marinas
2019-04-02 7:51 ` Zhangshaokun
2019-04-03 12:57 ` Catalin Marinas
2019-04-08 7:51 ` Zhangshaokun
2019-04-16 13:51 ` Will Deacon
2019-04-16 14:23 ` Zhangshaokun
2019-04-16 14:59 ` Catalin Marinas
2019-04-17 3:41 ` Zhangshaokun
2019-04-04 10:27 ` Catalin Marinas [this message]
2019-04-05 8:29 ` John Garry
2019-04-08 8:24 ` Zhangshaokun
2019-04-02 13:02 ` Suzuki K Poulose
2019-04-08 8:33 ` Zhangshaokun
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190404102756.GC43584@arrakis.emea.arm.com \
--to=catalin.marinas@arm.com \
--cc=Suzuki.Poulose@arm.com \
--cc=guohanjun@huawei.com \
--cc=john.garry@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=qiuzhenfa@hisilicon.com \
--cc=sudeep.holla@arm.com \
--cc=will.deacon@arm.com \
--cc=zhangshaokun@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).