From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A318C4360F for ; Thu, 4 Apr 2019 10:28:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD35920820 for ; Thu, 4 Apr 2019 10:28:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="cgSKmnOp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DD35920820 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Qdmek9+wzI0DW5zAW2zpNbZGcu8UqbEwUelH0cnZhag=; b=cgSKmnOpSn70No DsUE+jeWGcVIV0q7iQ7tho6KoEAmCKewHH9EwqEqgs/a/MEBJYc3mPVXmDTH33brTyZM/9Uxq5a8u zRb+77L14rPJTEaEjnRmfKeZEKNfw9sMDwIhF+IpdShy3PXQHh0Kh9tVkGlWMGNxuOVfsxWCL44rV OS5P3AxqG7mxsex+g8H0D2iZTth0U46/OCMM0CUTLeXxQyg+mP8tLMDUswHfOKHJ5IqTjU2nOS1CT wopvOvIflhUEHmoPe1GT5CQrumMIpDbDlF73wYwO6Z1tbd//iDcN4zAm+l9Ndaz0St6f36nmWCqLr nhrxJh7vRiJZBPFPaNtg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBzbI-0008Fs-IK; Thu, 04 Apr 2019 10:28:04 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hBzbG-0008FV-1u for linux-arm-kernel@lists.infradead.org; Thu, 04 Apr 2019 10:28:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E9F07168F; Thu, 4 Apr 2019 03:28:00 -0700 (PDT) Received: from arrakis.emea.arm.com (arrakis.cambridge.arm.com [10.1.196.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F5F83F557; Thu, 4 Apr 2019 03:27:59 -0700 (PDT) Date: Thu, 4 Apr 2019 11:27:56 +0100 From: Catalin Marinas To: Zhangshaokun Subject: Re: [PATCH] arm64: cache: Update cache_line_size for HiSilicon certain platform Message-ID: <20190404102756.GC43584@arrakis.emea.arm.com> References: <1553581690-24753-1-git-send-email-zhangshaokun@hisilicon.com> <20190326145510.GB33308@arrakis.emea.arm.com> <20190329185257.GD48010@arrakis.emea.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190404_032802_107644_E4A2565E X-CRM114-Status: GOOD ( 10.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sudeep Holla , Suzuki K Poulose , John Garry , Will Deacon , Zhenfa Qiu , Hanjun Guo , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 02, 2019 at 03:51:33PM +0800, Zhangshaokun wrote: > One more question about CWG, if cache line size of L1$ and L2$ on A76 is > 64-byte and it is used on our platform (L3C cache line is 128-byte), Shall > CWG is 4b'0100(64-byte) or 4'b0101(128-byte)? What does /sys/devices/system/cpu/cpu0/cache/index3/coherency_line_size say on your CPU? This would be information provided by firmware. Since cache_line_size() in Linux seems to be used for performance rather than DMA coherency (ARCH_DMA_MINALIGN is the one ensuring this), there may be a use-case for setting it based on the cache topology description in ACPI (PPTT) or DT (see drivers/base/cacheinfo.c; also cc'ing Sudeep since he contributed the cacheinfo code). But before we change anything in the arch code regarding cache_line_size(), we need a better understanding of why 128-byte makes a significant difference (does 256 make it even better?). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel