* [PATCH] perf vendor events arm64: Add Cortex-A72 events
@ 2019-04-07 21:34 Florian Fainelli
2019-04-08 16:47 ` Will Deacon
2019-04-11 13:01 ` John Garry
0 siblings, 2 replies; 5+ messages in thread
From: Florian Fainelli @ 2019-04-07 21:34 UTC (permalink / raw)
To: linux-kernel
Cc: Mark Rutland, Florian Fainelli, Peter Zijlstra, Catalin Marinas,
Will Deacon, Arnaldo Carvalho de Melo, Alexander Shishkin,
Ingo Molnar, Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
The Cortex-A72 supports all ARMv8 recommended events up to the
RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping
those events and update the mapfile.csv for matching the Cortex-A72 MIDR
to that file.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../arm64/arm/cortex-a72/core-imp-def.json | 206 ++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
2 files changed, 207 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
new file mode 100644
index 000000000000..eb82fc8529c6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
@@ -0,0 +1,206 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_TLB_WR",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NORMAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_PERIPH",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "DP_SPEC",
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC",
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC",
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC",
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC",
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF",
+ },
+ {
+ "ArchStdEvent": "EXC_SVC",
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ",
+ },
+ {
+ "ArchStdEvent": "EXC_SMC",
+ },
+ {
+ "ArchStdEvent": "EXC_HVC",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ",
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 59cd8604b0bd..716d59248e82 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,6 +13,7 @@
#
#Family-model,Version,Filename,EventType
0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
+0x00000000410fd08[[:xdigit:]],v1,arm/cortex-a72,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] perf vendor events arm64: Add Cortex-A72 events
2019-04-07 21:34 [PATCH] perf vendor events arm64: Add Cortex-A72 events Florian Fainelli
@ 2019-04-08 16:47 ` Will Deacon
2019-04-09 14:30 ` Florian Fainelli
2019-04-11 13:01 ` John Garry
1 sibling, 1 reply; 5+ messages in thread
From: Will Deacon @ 2019-04-08 16:47 UTC (permalink / raw)
To: Florian Fainelli
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, linux-kernel,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
Hi Florian,
On Sun, Apr 07, 2019 at 02:34:22PM -0700, Florian Fainelli wrote:
> The Cortex-A72 supports all ARMv8 recommended events up to the
> RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping
> those events and update the mapfile.csv for matching the Cortex-A72 MIDR
> to that file.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../arm64/arm/cortex-a72/core-imp-def.json | 206 ++++++++++++++++++
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> 2 files changed, 207 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
It would be worth checking how many of these events are common between a57
and a72, as they may be able to share much of the json file.
Cheers,
Will
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add Cortex-A72 events
2019-04-08 16:47 ` Will Deacon
@ 2019-04-09 14:30 ` Florian Fainelli
0 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2019-04-09 14:30 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, linux-kernel,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 4/8/2019 9:47 AM, Will Deacon wrote:
> Hi Florian,
>
> On Sun, Apr 07, 2019 at 02:34:22PM -0700, Florian Fainelli wrote:
>> The Cortex-A72 supports all ARMv8 recommended events up to the
>> RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping
>> those events and update the mapfile.csv for matching the Cortex-A72 MIDR
>> to that file.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>> .../arm64/arm/cortex-a72/core-imp-def.json | 206 ++++++++++++++++++
>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>> 2 files changed, 207 insertions(+)
>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>
> It would be worth checking how many of these events are common between a57
> and a72, as they may be able to share much of the json file.
Makes sense, will check the Cortex-A57 TRM and re-submit accordingly.
Thanks!
--
Florian
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add Cortex-A72 events
2019-04-07 21:34 [PATCH] perf vendor events arm64: Add Cortex-A72 events Florian Fainelli
2019-04-08 16:47 ` Will Deacon
@ 2019-04-11 13:01 ` John Garry
2019-05-02 21:41 ` Florian Fainelli
1 sibling, 1 reply; 5+ messages in thread
From: John Garry @ 2019-04-11 13:01 UTC (permalink / raw)
To: Florian Fainelli, linux-kernel
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, Will Deacon,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 07/04/2019 22:34, Florian Fainelli wrote:
> The Cortex-A72 supports all ARMv8 recommended events up to the
> RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping
> those events and update the mapfile.csv for matching the Cortex-A72 MIDR
> to that file.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> .../arm64/arm/cortex-a72/core-imp-def.json | 206 ++++++++++++++++++
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> 2 files changed, 207 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>
> diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
> new file mode 100644
> index 000000000000..eb82fc8529c6
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
> @@ -0,0 +1,206 @@
> +[
> + {
> + "ArchStdEvent": "L1D_CACHE_RD",
> + },
> + {
> + "ArchStdEvent": "L1D_CACHE_WR",
> + },
> + {
> + "ArchStdEvent": "L1D_CACHE_REFILL_RD",
> + },
> + {
> + "ArchStdEvent": "L1D_CACHE_REFILL_WR",
> + },
> + {
> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
I'm just checking the A72 TRM, and this does not seem to be included,
that being event number 0x44.
> + },
> + {
> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
> + },
Or this.
> + {
> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
> + },
> + {
Please check this.
Thanks,
John
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] perf vendor events arm64: Add Cortex-A72 events
2019-04-11 13:01 ` John Garry
@ 2019-05-02 21:41 ` Florian Fainelli
0 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2019-05-02 21:41 UTC (permalink / raw)
To: John Garry, linux-kernel
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, Will Deacon,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
Namhyung Kim, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 4/11/19 6:01 AM, John Garry wrote:
> On 07/04/2019 22:34, Florian Fainelli wrote:
>> The Cortex-A72 supports all ARMv8 recommended events up to the
>> RC_ST_SPEC (0x91) event, create an appropriate JSON file for mapping
>> those events and update the mapfile.csv for matching the Cortex-A72 MIDR
>> to that file.
>>
>> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
>> ---
>> .../arm64/arm/cortex-a72/core-imp-def.json | 206 ++++++++++++++++++
>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
>> 2 files changed, 207 insertions(+)
>> create mode 100644
>> tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>>
>> diff --git
>> a/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>> b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>> new file mode 100644
>> index 000000000000..eb82fc8529c6
>> --- /dev/null
>> +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a72/core-imp-def.json
>> @@ -0,0 +1,206 @@
>> +[
>> + {
>> + "ArchStdEvent": "L1D_CACHE_RD",
>> + },
>> + {
>> + "ArchStdEvent": "L1D_CACHE_WR",
>> + },
>> + {
>> + "ArchStdEvent": "L1D_CACHE_REFILL_RD",
>> + },
>> + {
>> + "ArchStdEvent": "L1D_CACHE_REFILL_WR",
>> + },
>> + {
>> + "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
>
> I'm just checking the A72 TRM, and this does not seem to be included,
> that being event number 0x44.
>
>> + },
>> + {
>> + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
>> + },
>
> Or this.
>
>> + {
>> + "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
>> + },
>> + {
>
> Please check this.
Indeed, thanks!
--
Florian
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
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2019-04-07 21:34 [PATCH] perf vendor events arm64: Add Cortex-A72 events Florian Fainelli
2019-04-08 16:47 ` Will Deacon
2019-04-09 14:30 ` Florian Fainelli
2019-04-11 13:01 ` John Garry
2019-05-02 21:41 ` Florian Fainelli
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