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From: Marc Zyngier <marc.zyngier@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Mark Rutland <mark.rutland@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Will Deacon <will.deacon@arm.com>
Subject: [PATCH 4/4] arm64: Apply ARM64_ERRATUM_1188873 to Neoverse-N1
Date: Mon,  8 Apr 2019 17:02:16 +0100	[thread overview]
Message-ID: <20190408160216.223871-5-marc.zyngier@arm.com> (raw)
In-Reply-To: <20190408160216.223871-1-marc.zyngier@arm.com>

Neoverse-N1 is also affected by ARM64_ERRATUM_1188873, so let's
add it to the list of affected CPUs.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm64/Kconfig             | 11 ++++++-----
 arch/arm64/kernel/cpu_errata.c | 13 +++++++++++--
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 560f2a860637..fcda4e21fa8f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -475,16 +475,17 @@ config ARM64_ERRATUM_1024718
 	  If unsure, say Y.
 
 config ARM64_ERRATUM_1188873
-	bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
+	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
 	default y
 	depends on COMPAT
 	select ARM_ARCH_TIMER_OOL_WORKAROUND
 	help
-	  This option adds work arounds for ARM Cortex-A76 erratum 1188873
+	  This option adds work arounds for ARM Cortex-A76/Neoverse-N1
+	  erratum 1188873
 
-	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
-	  register corruption when accessing the timer registers from
-	  AArch32 userspace.
+	  Affected Cortex-A76/Neoverse-N1 cores (r0p0, r1p0, r2p0) could
+	  cause register corruption when accessing the timer registers
+	  from AArch32 userspace.
 
 	  If unsure, say Y.
 
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 9950bb0cbd52..06f1c8aae1dc 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -603,6 +603,16 @@ static const struct midr_range workaround_clean_cache[] = {
 };
 #endif
 
+#ifdef CONFIG_ARM64_ERRATUM_1188873
+static const struct midr_range erratum_1188873_list[] = {
+	/* Cortex-A76 r0p0 to r2p0 */
+	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
+	/* Neoverse-N1 r0p0 to r2p0 */
+	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 2, 0),
+	{},
+};
+#endif
+
 const struct arm64_cpu_capabilities arm64_errata[] = {
 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 	{
@@ -725,10 +735,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_1188873
 	{
-		/* Cortex-A76 r0p0 to r2p0 */
 		.desc = "ARM erratum 1188873",
 		.capability = ARM64_WORKAROUND_1188873,
-		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
+		ERRATA_MIDR_RANGE_LIST(erratum_1188873_list),
 	},
 #endif
 #ifdef CONFIG_ARM64_ERRATUM_1165522
-- 
2.20.1


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      parent reply	other threads:[~2019-04-08 16:03 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-08 16:02 [PATCH 0/4] arm64: Rework handling of erratum 1188873 Marc Zyngier
2019-04-08 16:02 ` [PATCH 1/4] arm64: Restrict ARM64_ERRATUM_1188873 mitigation to AArch32 Marc Zyngier
2019-04-08 18:34   ` Robin Murphy
2019-04-09  9:18     ` Marc Zyngier
2019-04-09  9:49       ` Robin Murphy
2019-04-12 13:17   ` Will Deacon
2019-04-15  8:15     ` Marc Zyngier
2019-04-15  8:26       ` Daniel Lezcano
2019-04-08 16:02 ` [PATCH 2/4] arm64: Make ARM64_ERRATUM_1188873 depend on COMPAT Marc Zyngier
2019-04-08 16:02 ` [PATCH 3/4] arm64: Add part number for Neoverse N1 Marc Zyngier
2019-04-08 16:02 ` Marc Zyngier [this message]

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