From: Bjorn Helgaas <helgaas@kernel.org>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: mark.rutland@arm.com, heiko@sntech.de,
hayashi.kunihiko@socionext.com, tiwai@suse.de,
catalin.marinas@arm.com, spujar@nvidia.com, will.deacon@arm.com,
kthota@nvidia.com, mperttunen@nvidia.com,
thierry.reding@gmail.com, jonathanh@nvidia.com,
stefan.wahren@i2se.com, lorenzo.pieralisi@arm.com,
krzk@kernel.org, kishon@ti.com, maxime.ripard@bootlin.com,
jagan@amarulasolutions.com, linux-pci@vger.kernel.org,
andy.gross@linaro.org, shawn.lin@rock-chips.com,
devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
marc.w.gonzalez@free.fr, liviu.dudau@arm.com,
yue.wang@amlogic.com, enric.balletbo@collabora.com,
robh+dt@kernel.org, linux-tegra@vger.kernel.org,
horms+renesas@verge.net.au, bjorn.andersson@linaro.org,
ezequiel@collabora.com, linux-arm-kernel@lists.infradead.org,
xiaowei.bao@nxp.com, gustavo.pimentel@synopsys.com,
linux-kernel@vger.kernel.org, skomatineni@nvidia.com,
jingoohan1@gmail.com, olof@lixom.net, tpiepho@impinj.com,
l.stach@pengutronix.de
Subject: Re: [PATCH 09/10] PCI: tegra: Add Tegra194 PCIe support
Date: Tue, 9 Apr 2019 08:26:04 -0500 [thread overview]
Message-ID: <20190409132604.GA256045@google.com> (raw)
In-Reply-To: <40c97eaa-e37e-860e-111d-879a135d9f51@nvidia.com>
On Tue, Apr 09, 2019 at 05:00:53PM +0530, Vidya Sagar wrote:
> On 4/6/2019 12:28 AM, Bjorn Helgaas wrote:
> > On Fri, Apr 05, 2019 at 01:23:51AM +0530, Vidya Sagar wrote:
> > > On 4/3/2019 11:06 PM, Bjorn Helgaas wrote:
> > > > On Wed, Apr 03, 2019 at 03:13:09PM +0530, Vidya Sagar wrote:
> > > > > On 4/3/2019 12:01 AM, Bjorn Helgaas wrote:
> > > > > > On Tue, Apr 02, 2019 at 12:47:48PM +0530, Vidya Sagar wrote:
> > > > > > > On 3/30/2019 2:22 AM, Bjorn Helgaas wrote:
> > > > > > > > On Tue, Mar 26, 2019 at 08:43:26PM +0530, Vidya Sagar wrote:
> > > > > > > > > Add support for Synopsys DesignWare core IP based PCIe host controller
> > > > > > > > > present in Tegra194 SoC.
> > > > > >
> > > > > > - Why does this chip require pcie_pme_disable_msi()? The only other
> > > > > > use is a DMI quirk for "MSI Wind U-100", added by c39fae1416d5
> > > > > > ("PCI PM: Make it possible to force using INTx for PCIe PME
> > > > > > signaling").
> > > > >
> > > > > Because Tegra194 doesn't support raising PME interrupts through MSI line.
> > There's something wrong here. Either the question of how PME is
> > signaled is generic and the spec provides a way for the OS to discover
> > that method, or it's part of the device-specific architecture that
> > each host bridge driver has to know about its device. If the former,
> > we need to make the PCI core smart enough to figure it out. If the
> > latter, we need a better interface than this ad hoc
> > pcie_pme_disable_msi() thing. But if it is truly the latter, your
> > current code is sufficient and we can refine it over time.
>
> In case of Tegra194, it is the latter case.
This isn't a Tegra194 question; it's a question of whether this
behavior is covered by the PCIe spec.
> > What I suspect should happen eventually is the DWC driver should call
> > devm_pci_alloc_host_bridge() directly, as all the non-DWC drivers do.
> > That would require a little reorganization of the DWC data structures,
> > but it would be good to be more consistent.
> >
> > For now, I think stashing the pointer in pcie_port or dw_pcie would be
> > OK. I'm not 100% clear on the difference, but it looks like either
> > should be common across all the DWC drivers, which is what we want.
>
> Since dw_pcie is common for both root port and end point mode structures,
> I think it makes sense to keep the pointer in pcie_port as this structure
> is specific to root port mode of operation.
> I'll make a note to reorganize code to have devm_pci_alloc_host_bridge()
> used in the beginning itself to be inline with non-DWC implementations.
> But, I'll take it up later (after I'm done with upstreaming current series)
Fair enough.
> > > .remove() internally calls pm_runtime_put_sync() API which calls
> > > .runtime_suspend(). I made a new patch to add a host_deinit() call
> > > which make all these calls. Since host_init() is called from inside
> > > .runtime_resume() of this driver, to be in sync, I'm now calling
> > > host_deinit() from inside .runtime_suspend() API.
> >
> > I think this is wrong. pci_stop_root_bus() will detach all the
> > drivers from all the devices. We don't want to do that if we're
> > merely runtime suspending the host bridge, do we?
>
> In the current driver, the scenarios in which .runtime_suspend() is called
> are
> a) during .remove() call and
It makes sense that you should call pci_stop_root_bus() during
.remove(), i.e., when the host controller driver is being removed,
because the PCI bus will no longer be accessible. I think you should
call it *directly* from tegra_pcie_dw_remove() because that will match
what other drivers do.
> b) when there is no endpoint found and controller would be shutdown
> In both cases, it is required to stop the root bus and remove all devices,
> so, instead of having same call present in respective paths, I kept them
> in .runtime_suspend() itself to avoid code duplication.
I don't understand this part. We should be able to runtime suspend
the host controller without detaching drivers for child devices.
If you shutdown the controller completely and detach the *host
controller driver*, sure, it makes sense to detach drivers from child
devices. But that would be handled by the host controller .remove()
method, not by the runtime suspend method.
Bjorn
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next prev parent reply other threads:[~2019-04-09 13:26 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-26 15:13 [PATCH 00/10] Add Tegra194 PCIe support Vidya Sagar
2019-03-26 15:13 ` [PATCH 01/10] PCI: save pci_bus pointer in pcie_port structure Vidya Sagar
2019-03-28 7:18 ` Jisheng Zhang
2019-03-28 7:38 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 02/10] PCI: perform dbi regs write lock towards the end Vidya Sagar
2019-03-26 15:13 ` [PATCH 03/10] PCI: dwc: Move config space capability search API Vidya Sagar
2019-03-28 12:33 ` Thierry Reding
2019-04-01 11:46 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 04/10] PCI: Add #defines for PCIe spec r4.0 features Vidya Sagar
2019-03-26 15:13 ` [PATCH 05/10] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-03-27 10:10 ` Jon Hunter
2019-03-27 10:53 ` Vidya Sagar
2019-03-28 13:15 ` Thierry Reding
2019-04-01 10:01 ` Vidya Sagar
2019-04-01 15:07 ` Thierry Reding
2019-04-02 11:41 ` Vidya Sagar
2019-04-02 14:35 ` Thierry Reding
2019-04-03 6:22 ` Vidya Sagar
2019-04-02 19:21 ` Bjorn Helgaas
2019-03-31 6:42 ` Rob Herring
2019-04-01 11:18 ` Vidya Sagar
2019-04-01 14:31 ` Thierry Reding
2019-04-02 9:16 ` Vidya Sagar
2019-04-02 14:20 ` Thierry Reding
2019-04-03 5:29 ` Vidya Sagar
2019-04-08 18:29 ` Trent Piepho
2019-04-09 11:07 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 06/10] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-03-28 16:59 ` Thierry Reding
2019-04-01 12:37 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 07/10] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-03-26 15:13 ` [PATCH 08/10] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-04-03 8:05 ` Kishon Vijay Abraham I
2019-04-03 10:45 ` Vidya Sagar
2019-03-26 15:13 ` [PATCH 09/10] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-03-27 10:07 ` Jon Hunter
2019-03-29 20:52 ` Bjorn Helgaas
2019-04-02 7:17 ` Vidya Sagar
2019-04-02 14:14 ` Thierry Reding
2019-04-03 9:15 ` Vidya Sagar
2019-04-02 18:31 ` Bjorn Helgaas
2019-04-03 9:43 ` Vidya Sagar
2019-04-03 17:36 ` Bjorn Helgaas
2019-04-04 19:53 ` Vidya Sagar
2019-04-05 18:58 ` Bjorn Helgaas
2019-04-09 11:30 ` Vidya Sagar
2019-04-09 13:26 ` Bjorn Helgaas [this message]
2019-04-10 6:10 ` Vidya Sagar
2019-04-10 8:14 ` Liviu Dudau
2019-04-10 9:53 ` Vidya Sagar
2019-04-10 11:35 ` Liviu Dudau
2019-03-26 15:13 ` [PATCH 10/10] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar
2019-03-27 10:08 ` Jon Hunter
2019-03-27 10:12 ` Vidya Sagar
2019-03-27 12:26 ` Jon Hunter
2019-03-28 8:19 ` Jisheng Zhang
2019-04-01 12:45 ` Vidya Sagar
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