From: Simon Horman <horms@verge.net.au>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org,
Wolfram Sang <wsa+renesas@sang-engineering.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH/RFC] arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps
Date: Wed, 10 Apr 2019 11:27:13 +0200 [thread overview]
Message-ID: <20190410092712.4neevfmz4o666lrm@verge.net.au> (raw)
In-Reply-To: <20190408212628.GB23071@lunn.ch>
On Mon, Apr 08, 2019 at 11:26:28PM +0200, Andrew Lunn wrote:
> On Mon, Apr 08, 2019 at 10:31:48AM +0200, Simon Horman wrote:
> > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
> > August 24, 2018, the TX clock internal delay mode isn't supported
> > on R-Car E3 (r8a77990) and D3 (r8a77995).
> >
> > * TX clock internal delay mode is required for reliable 1Gbps communication
> > using the KSZ9031RNX phy present on the Ebisu and Draak boards.
>
> Hi Simon
>
> My reading of the KSZ9031RNX datasheet suggests the PHY can perform
> the delays. MMD address 2h, Register 8h - RGMII Clock Pad Skew.
>
> The PHY driver might even have the needed vendor specific DT
> properties.
>
> Have you look at using this?
Thanks for the suggestion Andrew, I will ask Renesas about this.
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prev parent reply other threads:[~2019-04-10 9:27 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-08 8:31 [PATCH/RFC] arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps Simon Horman
2019-04-08 8:41 ` Wolfram Sang
2019-04-08 9:45 ` Simon Horman
2019-04-08 10:56 ` Wolfram Sang
2019-04-08 21:26 ` Andrew Lunn
2019-04-10 9:27 ` Simon Horman [this message]
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