From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49A85C10F14 for ; Fri, 12 Apr 2019 16:46:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1747820850 for ; Fri, 12 Apr 2019 16:46:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sCXhnOwO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1747820850 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JfAFNRdxbC2BhK4fRymIOOpXgq+FLpLBWXwhtYo8JIE=; b=sCXhnOwOqjdvhL QnLHaj4RjmR9YiDssVT2A14hvk0/hnGcTuiz0kY+KI1kJLXu4o2CEaQnicvvTALfUiAvADFN8DHSE aU7H2ESSkmsp9m/wq/ODGmui/640SI9YmjORxspa2Tv2Zpaz6ACFqN9ONAp6VT6SKrAkH1mpo43fM DOGT7V9Qfh5cw1G7DCQv3UJzCIrxxDIbdsOPnu9tq0nQf55Ejea4uS+cs7IlMIe4tdkPs8XijUE01 Y7q52rEdfchjqSZMTNpL+aRlYiY3SRE3uWrwhMP6DLNdFIn5xbQpdFxcSlHRFVUOMFPfqGYYVw/I3 rHYX3AYpjQdx3elmELWg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEzJi-0002iY-PC; Fri, 12 Apr 2019 16:46:18 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hEzJg-0002iB-3D for linux-arm-kernel@lists.infradead.org; Fri, 12 Apr 2019 16:46:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 01D4D15AB; Fri, 12 Apr 2019 09:46:15 -0700 (PDT) Received: from red-moon (unknown [10.1.197.39]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4F40E3F718; Fri, 12 Apr 2019 09:46:11 -0700 (PDT) Date: Fri, 12 Apr 2019 17:45:34 +0100 From: Lorenzo Pieralisi To: Marc Zyngier Subject: Re: [PATCH 7/7] irqchip/al-msi: Add ACPI support Message-ID: <20190412164534.GA9071@red-moon> References: <1554035733-11827-1-git-send-email-hhhawa@amazon.com> <1554035733-11827-3-git-send-email-hhhawa@amazon.com> <86pnq65v48.wl-marc.zyngier@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190412_094616_149278_36EC9846 X-CRM114-Status: GOOD ( 26.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: catalin.marinas@arm.com, will.deacon@arm.com, jonnyc@amazon.com, ronenk@amazon.com, vaerov@amazon.com, linux@armlinux.org.uk, talel@amazon.com, linux-acpi@vger.kernel.org, alisaidi@amazon.com, lenb@kernel.org, jason@lakedaemon.net, antoine.tenart@bootlin.com, Zeev Zilberman , tglx@linutronix.de, hanochu@amazon.com, linux-arm-kernel@lists.infradead.org, barakw@amazon.com, Hanna Hawa , rjw@rjwysocki.net, linux-kernel@vger.kernel.org, tsahee@annapurnalabs.com, dwmw@amazon.co.uk Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Apr 12, 2019 at 01:08:00PM +0100, Marc Zyngier wrote: > Hi Zeev, > > On 04/04/2019 15:45, Zeev Zilberman wrote: > > Hi Marc, > > > > We have considered exposing our interrupt controller both via MADT > > OEM-specific entry and via DSDT. > > We've chosen MADT OEM-specific entry, because it seemed like a > > reasonable placeholder for custom interrupt controller, but we can move > > to DSDT, if this seems like a better way to represent it. > > > > Either way we chose, we'll need to solve the ordering issue of the > > drivers probing. > > The desired order of driver probing in the system, because of the > > dependencies, is: > > GIC -> AL MSIX controller driver -> PCI > > If we keep using MADT, we can't just use IRQCHIP_DECLARE, because there > > is no way we found to control ordering of MADT probing. So, GIC might be > > probed after our driver in this case. > > The reason we used early_initcall, is that the early_initcalls are > > invoked after MADT probing in the system (and before DSDT probing). > > > > If we move to using DSDT we need to solve the ordering problem from > > another direction - make sure that MSIX driver is probed before PCI. > > In the patches that were posted for xgene interrupt controller (and > > weren't accepted) we saw that they proposed to solve the same issue > > by modifying ACPI subsystem code by defining a new type for msi drivers > > and probing them before PCI drivers > > (https://patchwork.ozlabs.org/patch/818771/). > > From the feedback on that patch > > (https://patchwork.ozlabs.org/cover/818767/#1788415) it seemed that > > alternative solution is in the works, > > but we didn't manage to find any followup on this. > > > > We would be glad to hear what you propose for fixing the ordering issue > > and rework the patches accordingly. > > There are multiple issues here, but the main one is that you're trying > to do something that is completely contrary to the ACPI spec by > inventing a new interrupt controller. > > The use case for ACPI is quite simple: you have HW that matches the ACPI > spec, and everything will work out of the box. This means GICv2+GICv2m > or GICv3+ITS. There is zero space for creativity. Now, if you want your > own interrupt controller, the only choice is to stick with DT. That's > the place for weird and wonderful stuff that ACPI cannot support. > > We've been around the block with XGene, and every "solution" was just > utter crap, prone to failure and in the end unmaintainable. Anything > involving an initcall definitely falls into that category. > > I'll let Lorenzo speak his mind as the arm64 ACPI maintainer, but from > an irqchip perspective, I can't see how to support this unless we get > the ACPI spec to support this type of configuration. That's pretty much it, as a matter of fact there is not much we can do, actually it is a problem that {should have been/can be} solved first at ACPI spec level, every kludge we put together to fix eg Xgene ended up having implicit dependencies/requirements on firmware that are non-existing from an ACPI spec binding perspective (eg DSDT objects ordering). It is not a kernel problem, however we put it, we can't guess an IRQ controllers dependency that can't be described. Lorenzo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel