From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09A82C10F0E for ; Mon, 15 Apr 2019 14:07:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D0AE72087C for ; Mon, 15 Apr 2019 14:07:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="C1Z+EsU0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D0AE72087C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5+ptMy3FscMJzhHyd5EKaxYR2sroh2lzASHIjeyjx/M=; b=C1Z+EsU02Wu6lk L/l5VqX0nxypY9i/NNLa8EicSiCetyNRt1pfmX360XbNnjX2NY7h8S8vLvjAfwRrcYW8EcPM1+q26 H2sq9XwoE3gvZ8fIOHIP1iBr2PJ+tHgsGbXufAF5N0+Ey9RguKY5LgZRbRUVXX1aD05ssFOYlK4JL Kzs/t6Scz9JfhT8KJwZlIp7MuApoxKGJQf7JuIQzTvQrM/orp7k0SPHtmnViPH2512T0DthjjCWJK MwMQVF0aQ97iCnl4Wt40e50EMnEf9mIu7HDszfbwdKppeb22ad60qtyLZkIrp6hngPBCq1YvQZwXk D/P+hBpZB5Vn/MCos2yg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hG2GR-000366-Vn; Mon, 15 Apr 2019 14:07:15 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hG2GL-00033b-CE for linux-arm-kernel@lists.infradead.org; Mon, 15 Apr 2019 14:07:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 13F30374; Mon, 15 Apr 2019 07:07:09 -0700 (PDT) Received: from e107155-lin (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B51E3F721; Mon, 15 Apr 2019 07:07:08 -0700 (PDT) Date: Mon, 15 Apr 2019 15:07:02 +0100 From: Sudeep Holla To: Marek Bykowski Subject: Re: L3 cache way-locking memory zone Message-ID: <20190415140645.GA24249@e107155-lin> References: <20190415153849.358d78a9@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190415153849.358d78a9@gmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190415_070709_463507_DEBDE12F X-CRM114-Status: GOOD ( 13.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Sudeep Holla Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Apr 15, 2019 at 03:38:49PM +0200, Marek Bykowski wrote: > Hi All, > > Would the mainline be interested in definition/creation of the memory > zone to L3 cache way-locking memory range/s? > > We have this implemented around the system featuring Cortex-A53/57 and > the CCN-512/504 with L3 cache (LLC) configured to way-locking. The > benefits arising are a faster memory access. > > If you reckon this is something of interest I can share more > details, patch, use case, etc. > I am sure many will be interested. But depends on how generic is the solution ? It's extremely difficult to come up with one. ARM has Memory System Resource Partitioning(MPAM) to solve this in a generic way. I know it may not solve issue for current platforms, but just thought it's worth pointing out so that people are aware of it. -- Regards, Sudeep _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel