From: Marek Bykowski <marek.bykowski@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Subject: L3 cache way-locking memory zone
Date: Mon, 15 Apr 2019 15:38:49 +0200 [thread overview]
Message-ID: <20190415153849.358d78a9@gmail.com> (raw)
Hi All,
Would the mainline be interested in definition/creation of the memory
zone to L3 cache way-locking memory range/s?
We have this implemented around the system featuring Cortex-A53/57 and
the CCN-512/504 with L3 cache (LLC) configured to way-locking. The
benefits arising are a faster memory access.
If you reckon this is something of interest I can share more
details, patch, use case, etc.
Thanks,
Marek
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next reply other threads:[~2019-04-15 13:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-15 13:38 Marek Bykowski [this message]
2019-04-15 14:07 ` L3 cache way-locking memory zone Sudeep Holla
2019-04-16 10:32 ` Marek Bykowski
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