[PATCH 1/2] nvmem: imx-ocotp: imx8m is compatible with imx6 not imx7

[PATCH 1/2] nvmem: imx-ocotp: imx8m is compatible with imx6 not imx7

[Leonard Crestez]

According to NXP Reference Manuals and uboot/atf sources the OCOTP block
on imx8m behaves more like imx6 than imx7.

- Fuses can be read/written 32bits at a time (no imx7-like banking)
- The OCOTP_HW_OCOTP_TIMING register is like imx6 not imx7

Since nvmem doesn't support uboot-style "sense" and "override" this
issue only affected "write" which is very rarely used.

Fixes: 163c0dbd0cb1 ("nvmem: imx-ocotp: add support for imx8mq")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 drivers/nvmem/imx-ocotp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index 4cf7b61e4bf5..c3e1d9d8a537 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -444,12 +444,12 @@ static const struct ocotp_params imx7ulp_params = {
 	.bank_address_words = 0,
 };
 
 static const struct ocotp_params imx8mq_params = {
 	.nregs = 256,
-	.bank_address_words = 4,
-	.set_timing = imx_ocotp_set_imx7_timing,
+	.bank_address_words = 0,
+	.set_timing = imx_ocotp_set_imx6_timing,
 };
 
 static const struct of_device_id imx_ocotp_dt_ids[] = {
 	{ .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
 	{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
-- 
2.17.1

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[PATCH 2/2] arm64: defconfig: NVMEM_IMX_OCOTP=y for imx8m

[Leonard Crestez]

Enable imx-ocotp nvmem driver for fuse access on imx8m family.

Tested on imx8mm-evk.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 483d0e251f37..a308869ecdf4 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -745,10 +745,11 @@ CONFIG_PHY_UNIPHIER_USB2=y
 CONFIG_PHY_UNIPHIER_USB3=y
 CONFIG_PHY_TEGRA_XUSB=y
 CONFIG_HISI_PMU=y
 CONFIG_QCOM_L2_PMU=y
 CONFIG_QCOM_L3_PMU=y
+CONFIG_NVMEM_IMX_OCOTP=y
 CONFIG_QCOM_QFPROM=y
 CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_UNIPHIER_EFUSE=y
 CONFIG_MESON_EFUSE=m
 CONFIG_TEE=y
-- 
2.17.1

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RE: [PATCH 2/2] arm64: defconfig: NVMEM_IMX_OCOTP=y for imx8m

[Peng Fan]

> Subject: [PATCH 2/2] arm64: defconfig: NVMEM_IMX_OCOTP=y for imx8m
> 
> Enable imx-ocotp nvmem driver for fuse access on imx8m family.
> 
> Tested on imx8mm-evk.
> 
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 483d0e251f37..a308869ecdf4 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -745,10 +745,11 @@ CONFIG_PHY_UNIPHIER_USB2=y
> CONFIG_PHY_UNIPHIER_USB3=y  CONFIG_PHY_TEGRA_XUSB=y
> CONFIG_HISI_PMU=y  CONFIG_QCOM_L2_PMU=y
> CONFIG_QCOM_L3_PMU=y
> +CONFIG_NVMEM_IMX_OCOTP=y
>  CONFIG_QCOM_QFPROM=y
>  CONFIG_ROCKCHIP_EFUSE=y
>  CONFIG_UNIPHIER_EFUSE=y
>  CONFIG_MESON_EFUSE=m
>  CONFIG_TEE=y

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> --
> 2.17.1

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Re: [PATCH 2/2] arm64: defconfig: NVMEM_IMX_OCOTP=y for imx8m

[Shawn Guo]

On Thu, Apr 18, 2019 at 09:42:48PM +0000, Leonard Crestez wrote:
> Enable imx-ocotp nvmem driver for fuse access on imx8m family.
> 
> Tested on imx8mm-evk.
> 
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>

Applied, thanks.

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RE: [PATCH 1/2] nvmem: imx-ocotp: imx8m is compatible with imx6 not imx7

[Peng Fan]

> Subject: [PATCH 1/2] nvmem: imx-ocotp: imx8m is compatible with imx6 not
> imx7
> 
> According to NXP Reference Manuals and uboot/atf sources the OCOTP block
> on imx8m behaves more like imx6 than imx7.
> 
> - Fuses can be read/written 32bits at a time (no imx7-like banking)
> - The OCOTP_HW_OCOTP_TIMING register is like imx6 not imx7
> 
> Since nvmem doesn't support uboot-style "sense" and "override" this issue
> only affected "write" which is very rarely used.
> 
> Fixes: 163c0dbd0cb1 ("nvmem: imx-ocotp: add support for imx8mq")
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
>  drivers/nvmem/imx-ocotp.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index
> 4cf7b61e4bf5..c3e1d9d8a537 100644
> --- a/drivers/nvmem/imx-ocotp.c
> +++ b/drivers/nvmem/imx-ocotp.c
> @@ -444,12 +444,12 @@ static const struct ocotp_params imx7ulp_params
> = {
>  	.bank_address_words = 0,
>  };
> 
>  static const struct ocotp_params imx8mq_params = {
>  	.nregs = 256,
> -	.bank_address_words = 4,
> -	.set_timing = imx_ocotp_set_imx7_timing,
> +	.bank_address_words = 0,
> +	.set_timing = imx_ocotp_set_imx6_timing,
>  };

Reviewed-by: Peng Fan <peng.fan@nxp.com>

> 
>  static const struct of_device_id imx_ocotp_dt_ids[] = {
>  	{ .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
>  	{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
> --
> 2.17.1

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Re: [PATCH 1/2] nvmem: imx-ocotp: imx8m is compatible with imx6 not imx7

[Bryan O'Donoghue]

On 18/04/2019 22:42, Leonard Crestez wrote:
> According to NXP Reference Manuals and uboot/atf sources the OCOTP block
> on imx8m behaves more like imx6 than imx7.
> 
> - Fuses can be read/written 32bits at a time (no imx7-like banking)
> - The OCOTP_HW_OCOTP_TIMING register is like imx6 not imx7
> 
> Since nvmem doesn't support uboot-style "sense" and "override" this
> issue only affected "write" which is very rarely used.
> 
> Fixes: 163c0dbd0cb1 ("nvmem: imx-ocotp: add support for imx8mq")
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
>   drivers/nvmem/imx-ocotp.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
> index 4cf7b61e4bf5..c3e1d9d8a537 100644
> --- a/drivers/nvmem/imx-ocotp.c
> +++ b/drivers/nvmem/imx-ocotp.c
> @@ -444,12 +444,12 @@ static const struct ocotp_params imx7ulp_params = {
>   	.bank_address_words = 0,
>   };
>   
>   static const struct ocotp_params imx8mq_params = {
>   	.nregs = 256,
> -	.bank_address_words = 4,
> -	.set_timing = imx_ocotp_set_imx7_timing,
> +	.bank_address_words = 0,
> +	.set_timing = imx_ocotp_set_imx6_timing,
>   };
>   
>   static const struct of_device_id imx_ocotp_dt_ids[] = {
>   	{ .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
>   	{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
> 

Err.

I believe you are missing a few bits here.

Let me send through a patch-set I just completed this morning

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