Re: [RESEND PATCH 0/7] Introduce bus domains controller framework

From: Sudeep Holla <sudeep.holla@arm.com>
To: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Rob Herring <robh@kernel.org>,
	Benjamin Gaignard <benjamin.gaignard@st.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	s.hauer@pengutronix.de,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Mark Brown <broonie@kernel.org>,
	linux-imx@nxp.com, kernel@pengutronix.de,
	Sudeep Holla <sudeep.holla@arm.com>,
	Fabio Estevam <fabio.estevam@nxp.com>,
	Loic PALLARDY <loic.pallardy@st.com>,
	Shawn Guo <shawnguo@kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [RESEND PATCH 0/7] Introduce bus domains controller framework
Date: Tue, 23 Apr 2019 14:21:26 +0100	[thread overview]
Message-ID: <20190423132116.GA3892@e107155-lin> (raw)
In-Reply-To: <CA+M3ks6bsiGXCKEQmaFmzBRhWPVhV5wBjVhgyfCa-25DohnsOg@mail.gmail.com>

On Mon, Mar 18, 2019 at 12:05:54PM +0100, Benjamin Gaignard wrote:
> Le lun. 18 mars 2019 à 11:43, Sudeep Holla <sudeep.holla@arm.com> a écrit :
> >
> > On Mon, Mar 18, 2019 at 11:05:58AM +0100, Benjamin Gaignard wrote:
> > > Bus domains controllers allow to divided system on chip into multiple domains
> > > that can be used to select by who hardware blocks could be accessed.
> > > A domain could be a cluster of CPUs (or coprocessors), a range of addresses or
> > > a group of hardware blocks.
> > >
> > > Framework architecture is inspirated by pinctrl framework:
> > > - a default configuration could be applied before bind the driver
> > > - configurations could be apllied dynamically by drivers
> > > - device node provides the bus domains configurations
> > >
> > > An example of bus domains controller is STM32 ETZPC hardware block
> > > which got 3 domains:
> > > - secure: hardware blocks are only accessible by software running on trust
> > >   zone.
> > > - non-secure: hardware blocks are accessible by non-secure software (i.e.
> > >   linux kernel).
> > > - coprocessor: hardware blocks are only accessible by the corpocessor.
> > > Up to 94 hardware blocks of the soc could be managed by ETZPC and
> > > assigned to one of the three domains.
> > >
> >
> > You fail to explain why do we need this in non-secure Linux ?
> > You need to have solid reasons as why this can't be done in secure
> > firmware. And yes I mean even on arm32. On platforms with such hardware
> > capabilities you will need some secure firmware to be running and these
> > things can be done there. I don't want this enabled for ARM64 at all,
> > firmware *has to deal* with this.
>
> We use ETZPC to define if hardware blocks can be used by Cortex A7 or Cortex
> M4 (both non-secure) on STM32MP1 SoC, this new framework allow to change
> hardware block split at runtime. This could be done even on non-secure world
> because their is nothing critical to change hardware blocks users.

OK, that's interesting, assuming Cortex M4 execution as non-secure. I would
expect otherwise. Even if it's configurable, I would see that happen in
secure entity via OPTEE or something similar from non-secure side.

Do you have any documents that I can refer to get the overall security
design for such platforms ?

--
Regards,
Sudeep

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