* [PATCH v2] ARM: errata: Workaround errata A12 857271 / A17 857272
@ 2019-04-23 22:59 Douglas Anderson
2019-04-26 22:37 ` Doug Anderson
0 siblings, 1 reply; 2+ messages in thread
From: Douglas Anderson @ 2019-04-23 22:59 UTC (permalink / raw)
To: Russell King
Cc: mark.rutland, Douglas Anderson, heiko, Tony Lindgren,
Palmer Dabbelt, will.deacon, bbatacha, Masahiro Yamada,
Lorenzo Pieralisi, linux-rockchip, mka, Salva.Climent,
Arnd Bergmann, marc.w.gonzalez, Marc Zyngier, sonnyrao,
linux-arm-kernel, Ard Biesheuvel, linux-kernel, Paul Burton,
Andrew Morton, robin.murphy
This adds support for working around errata A12 857271 / A17 857272.
These errata were causing hangs on rk3288-based Chromebooks and it was
confirmed that this workaround fixed the problems. In the Chrome OS
3.14 kernel this was treated as two errata: ERRATA_FOOBAR [1] and
ERRATA_CR711784 [2]. Apparently the two errata got lumped together at
some point in time.
Let's actually get the workaround landed.
[1] https://crrev.com/c/342753
[2] https://crbug.com/711784
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
---
Changes in v2:
- Squashed bits 10 and 11 into one errata.
arch/arm/Kconfig | 18 ++++++++++++++++++
arch/arm/mm/proc-v7.S | 10 ++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b509cd338219..59fdcd51d7ee 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1172,6 +1172,14 @@ config ARM_ERRATA_825619
DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
and Device/Strongly-Ordered loads and stores might cause deadlock
+config ARM_ERRATA_857271
+ bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 857271 Cortex-A12
+ (all revs) erratum. Under very rare timing conditions, the CPU might
+ hang. The workaround is expected to have a < 1% performance impact.
+
config ARM_ERRATA_852421
bool "ARM errata: A17: DMB ST might fail to create order between stores"
depends on CPU_V7
@@ -1193,6 +1201,16 @@ config ARM_ERRATA_852423
config option from the A12 erratum due to the way errata are checked
for and handled.
+config ARM_ERRATA_857272
+ bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 857272 Cortex-A17 erratum.
+ This erratum is not known to be fixed in any A17 revision.
+ This is identical to Cortex-A12 erratum 857271. It is a separate
+ config option from the A12 erratum due to the way errata are checked
+ for and handled.
+
endmenu
source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 339eb17c9808..2966086d8a45 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -391,6 +391,11 @@ __ca12_errata:
mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
orr r10, r10, #1 << 24 @ set bit #24
mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
+#endif
+#ifdef CONFIG_ARM_ERRATA_857271
+ mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
+ orr r10, r10, #3 << 10 @ set bits #10 and #11
+ mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
b __errata_finish
@@ -406,6 +411,11 @@ __ca17_errata:
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
orrle r10, r10, #1 << 12 @ set bit #12
mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
+#endif
+#ifdef CONFIG_ARM_ERRATA_857272
+ mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
+ orr r10, r10, #3 << 10 @ set bits #10 and #11
+ mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
b __errata_finish
--
2.21.0.593.g511ec345e18-goog
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] ARM: errata: Workaround errata A12 857271 / A17 857272
2019-04-23 22:59 [PATCH v2] ARM: errata: Workaround errata A12 857271 / A17 857272 Douglas Anderson
@ 2019-04-26 22:37 ` Doug Anderson
0 siblings, 0 replies; 2+ messages in thread
From: Doug Anderson @ 2019-04-26 22:37 UTC (permalink / raw)
To: Russell King
Cc: Mark Rutland, Lorenzo Pieralisi, Jose Salvador Climent Bayarri,
Arnd Bergmann, Marc Gonzalez, Masahiro Yamada, Robin Murphy,
Palmer Dabbelt, Will Deacon, Bobby Batacharia, LKML,
Ard Biesheuvel, open list:ARM/Rockchip SoC..., Paul Burton,
Matthias Kaehlcke, Tony Lindgren, Marc Zyngier, Andrew Morton,
Sonny Rao, Linux ARM, Heiko Stübner
Hi,
On Tue, Apr 23, 2019 at 4:00 PM Douglas Anderson <dianders@chromium.org> wrote:
>
> This adds support for working around errata A12 857271 / A17 857272.
> These errata were causing hangs on rk3288-based Chromebooks and it was
> confirmed that this workaround fixed the problems. In the Chrome OS
> 3.14 kernel this was treated as two errata: ERRATA_FOOBAR [1] and
> ERRATA_CR711784 [2]. Apparently the two errata got lumped together at
> some point in time.
>
> Let's actually get the workaround landed.
>
> [1] https://crrev.com/c/342753
> [2] https://crbug.com/711784
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
> ---
>
> Changes in v2:
> - Squashed bits 10 and 11 into one errata.
>
> arch/arm/Kconfig | 18 ++++++++++++++++++
> arch/arm/mm/proc-v7.S | 10 ++++++++++
> 2 files changed, 28 insertions(+)
Breadcrumbs: this has been submitted to RMK's patch tracking system. See:
https://www.armlinux.org.uk/developer/patches/viewpatch.php?id=8861/1
-Doug
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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