From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92D75C43219 for ; Thu, 25 Apr 2019 13:28:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 42156216B7 for ; Thu, 25 Apr 2019 13:28:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uHP+9R6J" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42156216B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cbYpcedoC00spKLVSpUPEaBM6OPodvSh2qHRnffN8L4=; b=uHP+9R6JnGeQfV URF7MgFasZIJIjCTjX3xyhH+jwsdiReRmoHoRv/TXpMkYFUX70Z4dkFEVuuMxvrJAibNfB7Tajswq uoyNS0UITNmIM/v25b2df3Vfa3fUwDPyeWg67z8jPO4HV6gb08XUmm8CA/+6LlEFa8K0CQAWDGXd5 ZbQBqmO9M6483PvwmxF9+Y6lBDa9lSrTMlEeEB7b/trSfoaewJRtNjLHAkZear0DZ5JPZ1k6dI97/ colF+zC8HDJVqahgS5gskXJCd6gz02mMOs+29bwNUoM9Z2A6jiDE5nUKyYdRuM/skkEVSVSQapeuv GjMHzd+TCzaWhFvDxOzA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hJeQB-0004KX-KZ; Thu, 25 Apr 2019 13:28:15 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hJeQ8-0004K2-PZ for linux-arm-kernel@lists.infradead.org; Thu, 25 Apr 2019 13:28:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE675A78; Thu, 25 Apr 2019 06:28:10 -0700 (PDT) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BA0A13F5C1; Thu, 25 Apr 2019 06:28:08 -0700 (PDT) Date: Thu, 25 Apr 2019 14:28:06 +0100 From: Dave Martin To: Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH v7 12/27] KVM: arm64/sve: System register context switch and access support Message-ID: <20190425132805.GC3567@e103592.cambridge.arm.com> References: <1553864452-15080-1-git-send-email-Dave.Martin@arm.com> <1553864452-15080-13-git-send-email-Dave.Martin@arm.com> <87bm0vwhsd.fsf@zen.linaroharston> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87bm0vwhsd.fsf@zen.linaroharston> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_062812_840815_84669BE0 X-CRM114-Status: GOOD ( 30.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Zhang Lei , Julien Grall , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 24, 2019 at 04:21:22PM +0100, Alex Benn=E9e wrote: > = > Dave Martin writes: > = > > This patch adds the necessary support for context switching ZCR_EL1 > > for each vcpu. > > > > ZCR_EL1 is trapped alongside the FPSIMD/SVE registers, so it makes > > sense for it to be handled as part of the guest FPSIMD/SVE context > > for context switch purposes instead of handling it as a general > > system register. This means that it can be switched in lazily at > > the appropriate time. No effort is made to track host context for > > this register, since SVE requires VHE: thus the hosts's value for > > this register lives permanently in ZCR_EL2 and does not alias the > > guest's value at any time. > > > > The Hyp switch and fpsimd context handling code is extended > > appropriately. > > > > Accessors are added in sys_regs.c to expose the SVE system > > registers and ID register fields. Because these need to be > > conditionally visible based on the guest configuration, they are > > implemented separately for now rather than by use of the generic > > system register helpers. This may be abstracted better later on > > when/if there are more features requiring this model. > > > > ID_AA64ZFR0_EL1 is RO-RAZ for MRS/MSR when SVE is disabled for the > > guest, but for compatibility with non-SVE aware KVM implementations > > the register should not be enumerated at all for KVM_GET_REG_LIST > > in this case. For consistency we also reject ioctl access to the > > register. This ensures that a non-SVE-enabled guest looks the same > > to userspace, irrespective of whether the kernel KVM implementation > > supports SVE. > > > > Signed-off-by: Dave Martin > > Reviewed-by: Julien Thierry > > Tested-by: zhang.lei > > > > --- > > [...] > > diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c > > index 1cf4f02..7053bf4 100644 > > --- a/arch/arm64/kvm/fpsimd.c > > +++ b/arch/arm64/kvm/fpsimd.c > > @@ -103,14 +103,21 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vc= pu) > > void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu) > > { > > unsigned long flags; > > + bool host_has_sve =3D system_supports_sve(); > > + bool guest_has_sve =3D vcpu_has_sve(vcpu); > > > > local_irq_save(flags); > > > > if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) { > > + u64 *guest_zcr =3D &vcpu->arch.ctxt.sys_regs[ZCR_EL1]; > > + > = > Is this just to avoid: > = > vcpu->arch.ctxt.sys_regs[ZCR_EL1] =3D read_sysreg_s(SYS_ZCR_EL12); No, it's just done to shorten the line. Otherwise a trailing =3D is hard to avoid (which Marc didn't like) or the line has to be over 80 chars (which I didn't like). > in fact wouldn't: > = > __vcpu_sys_reg(vcpu,ZCR_EL1) =3D read_sysreg_s(SYS_ZCR_EL12); We could use __vcpu_sys_reg() yes, I missed that. I could spin a patch for this, but it doesn't feel like a high priority at this stage. [...] > Reviewed-by: Alex Benn=E9e Thanks ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel