From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEF42C04AA7 for ; Mon, 13 May 2019 11:19:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7EE52208CA for ; Mon, 13 May 2019 11:19:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ruxtpMJ2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7EE52208CA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Io59MIK5AuHOtzaC5bWXAKST/5g3MGJQD0clHSedFJQ=; b=ruxtpMJ28ZZAPY SAmE51QR3Wp5ugl2hUJLLOHEOPT+OpOU+3A9Zv6pAnViLqzYALl/9WuQq3/Kjg9utZV42z8JsYyoC 0Zn4iIv3H6lNqEVL5j7ouCXVhpfcLVNExqPtBQOJwM/yXDSNOczUBKX31/hipkmu+1gVj+eQhbPja PiZvXp2tCZVhaZB58JOq44+1MFcyNyj5kdPp0bQpLDpNZiKpt+siolOaITk2PwWvcaYoxoNZagxbD f6KxFRIV7wCWjONxpHChewrJHMuE7Dca6nQdHTmz2DeYN6971VEhyWp9a+UsH7ethFpeSlMnIcx9y gwFY9tlB4yzlSE+Gi8mA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hQ8za-0003q6-71; Mon, 13 May 2019 11:19:38 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hQ8zX-0003pl-3o for linux-arm-kernel@lists.infradead.org; Mon, 13 May 2019 11:19:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FC0D374; Mon, 13 May 2019 04:19:34 -0700 (PDT) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7B8543F703; Mon, 13 May 2019 04:19:32 -0700 (PDT) Date: Mon, 13 May 2019 12:19:30 +0100 From: Will Deacon To: Florian Fainelli Subject: Re: [PATCH v2] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Message-ID: <20190513111930.GD6711@fuggles.cambridge.arm.com> References: <20190502234704.7663-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190502234704.7663-1-f.fainelli@gmail.com> User-Agent: Mutt/1.11.1+86 (6f28e57d73f2) () X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190513_041935_168881_DF958011 X-CRM114-Status: GOOD ( 12.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Peter Zijlstra , Catalin Marinas , john.garry@huawei.com, linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Alexander Shishkin , Ingo Molnar , Namhyung Kim , Jiri Olsa , "moderated list:ARM PMU PROFILING AND DEBUGGING" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 02, 2019 at 04:47:04PM -0700, Florian Fainelli wrote: > diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv > index 59cd8604b0bd..69a73957e35c 100644 > --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv > +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv > @@ -13,6 +13,8 @@ > # > #Family-model,Version,Filename,EventType > 0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core > +0x00000000411fd07[[:xdigit:]],v1,arm/cortex-a57-a72,core The 4-bit variant field should be 0x0, not 0x1. In fact, I think we could do the same for the revision field too and use 0x0 instead of [[:xdigit:]] for Cortex-A53, no? Our implementation of get_cpuid_str() masks these out for us. Am I missing something? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel