* [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72
@ 2019-05-13 20:25 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Mark Rutland, Florian Fainelli, Peter Zijlstra, Catalin Marinas,
John Garry, Will Deacon, Arnaldo Carvalho de Melo,
Alexander Shishkin, Ingo Molnar, Ganapatrao Kulkarni,
Namhyung Kim, Sean V Kelley, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
Hi all,
Based on discussion about the last patch, it turned out that we can
remove the [[:xdigit:]] wildcard entirely since get_cpuid_str() strips
the revision bits anyway.
Florian Fainelli (3):
perf vendor events arm64: Remove [[:xdigit:]] wildcard
perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events
perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
.../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 5 +-
2 files changed, 183 insertions(+), 1 deletion(-)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
--
2.17.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
@ 2019-05-13 20:25 ` Florian Fainelli
2019-05-15 9:02 ` John Garry
2019-05-13 20:25 ` [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events Florian Fainelli
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Mark Rutland, Florian Fainelli, Peter Zijlstra, Catalin Marinas,
John Garry, Will Deacon, Arnaldo Carvalho de Melo,
Alexander Shishkin, Ingo Molnar, Ganapatrao Kulkarni,
Namhyung Kim, Sean V Kelley, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
ARM64's implementation of get_cpuidr_str() masks out the revision bits
[3:0] while reading the CPU identifier, there is no need for the
[[:xdigit:]] wildcard.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 59cd8604b0bd..da5ff2204bf6 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -12,7 +12,7 @@
#
#
#Family-model,Version,Filename,EventType
-0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
+0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
@ 2019-05-13 20:25 ` Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
2019-05-15 19:13 ` [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Arnaldo Carvalho de Melo
3 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Mark Rutland, Florian Fainelli, Alexander Shishkin,
Catalin Marinas, John Garry, Will Deacon,
Arnaldo Carvalho de Melo, Arnaldo Carvalho de Melo,
Peter Zijlstra, Ingo Molnar, bcm-kernel-feedback-list,
Ganapatrao Kulkarni, Namhyung Kim, Sean V Kelley, Jiri Olsa,
linux-arm-kernel
Broadcom's Brahma-B53 CPUs support the same type of events that the
Cortex-A53 supports, recognize its CPUID and map it to the cortex-a53
events.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-arm-kernel@lists.infradead.org (moderated list:arm pmu profiling and debugging)
Link: http://lkml.kernel.org/r/20190405165047.15847-1-f.fainelli@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index da5ff2204bf6..013155f1eb58 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -13,6 +13,7 @@
#
#Family-model,Version,Filename,EventType
0x00000000410fd030,v1,arm/cortex-a53,core
+0x00000000420f1000,v1,arm/cortex-a53,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events Florian Fainelli
@ 2019-05-13 20:25 ` Florian Fainelli
2019-05-15 19:13 ` [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Arnaldo Carvalho de Melo
3 siblings, 0 replies; 6+ messages in thread
From: Florian Fainelli @ 2019-05-13 20:25 UTC (permalink / raw)
To: linux-kernel
Cc: Mark Rutland, Florian Fainelli, Peter Zijlstra, Catalin Marinas,
John Garry, Will Deacon, Arnaldo Carvalho de Melo,
Alexander Shishkin, Ingo Molnar, Ganapatrao Kulkarni,
Namhyung Kim, Sean V Kelley, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events
up to the RC_ST_SPEC (0x91) event with the exception of:
- L1D_CACHE_REFILL_INNER (0x44)
- L1D_CACHE_REFILL_OUTER (0x45)
- L1D_TLB_RD (0x4E)
- L1D_TLB_WR (0x4F)
- L2D_TLB_REFILL_RD (0x5C)
- L2D_TLB_REFILL_WR (0x5D)
- L2D_TLB_RD (0x5E)
- L2D_TLB_WR (0x5F)
- STREX_SPEC (0x6F)
Create an appropriate JSON file for mapping those events and update the
mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that
file.
Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
.../arm/cortex-a57-a72/core-imp-def.json | 179 ++++++++++++++++++
tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +
2 files changed, 181 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
new file mode 100644
index 000000000000..0ac9b7927450
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json
@@ -0,0 +1,179 @@
+[
+ {
+ "ArchStdEvent": "L1D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L1D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NORMAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_PERIPH",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC",
+ },
+ {
+ "ArchStdEvent": "LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "DP_SPEC",
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC",
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC",
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC",
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC",
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF",
+ },
+ {
+ "ArchStdEvent": "EXC_SVC",
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ",
+ },
+ {
+ "ArchStdEvent": "EXC_SMC",
+ },
+ {
+ "ArchStdEvent": "EXC_HVC",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ",
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC",
+ },
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
index 013155f1eb58..927fcddcb4aa 100644
--- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -14,6 +14,8 @@
#Family-model,Version,Filename,EventType
0x00000000410fd030,v1,arm/cortex-a53,core
0x00000000420f1000,v1,arm/cortex-a53,core
+0x00000000410fd070,v1,arm/cortex-a57-a72,core
+0x00000000410fd080,v1,arm/cortex-a57-a72,core
0x00000000420f5160,v1,cavium/thunderx2,core
0x00000000430f0af0,v1,cavium/thunderx2,core
0x00000000480fd010,v1,hisilicon/hip08,core
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
@ 2019-05-15 9:02 ` John Garry
0 siblings, 0 replies; 6+ messages in thread
From: John Garry @ 2019-05-15 9:02 UTC (permalink / raw)
To: Florian Fainelli, linux-kernel
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, Will Deacon,
Arnaldo Carvalho de Melo, Alexander Shishkin, Ingo Molnar,
Ganapatrao Kulkarni, Namhyung Kim, Sean V Kelley, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
On 13/05/2019 21:25, Florian Fainelli wrote:
> ARM64's implementation of get_cpuidr_str() masks out the revision bits
> [3:0] while reading the CPU identifier, there is no need for the
> [[:xdigit:]] wildcard.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> index 59cd8604b0bd..da5ff2204bf6 100644
> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> @@ -12,7 +12,7 @@
> #
JFYI, this was discussed before, but this a53 entry seemed to make it
though:
https://lkml.org/lkml/2018/3/7/1236
> #
> #Family-model,Version,Filename,EventType
> -0x00000000410fd03[[:xdigit:]],v1,arm/cortex-a53,core
> +0x00000000410fd030,v1,arm/cortex-a53,core
> 0x00000000420f5160,v1,cavium/thunderx2,core
> 0x00000000430f0af0,v1,cavium/thunderx2,core
> 0x00000000480fd010,v1,hisilicon/hip08,core
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72
2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
` (2 preceding siblings ...)
2019-05-13 20:25 ` [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
@ 2019-05-15 19:13 ` Arnaldo Carvalho de Melo
3 siblings, 0 replies; 6+ messages in thread
From: Arnaldo Carvalho de Melo @ 2019-05-15 19:13 UTC (permalink / raw)
To: Florian Fainelli
Cc: Mark Rutland, Peter Zijlstra, Catalin Marinas, John Garry,
Will Deacon, linux-kernel, Alexander Shishkin, Ingo Molnar,
Ganapatrao Kulkarni, Namhyung Kim, Sean V Kelley, Jiri Olsa,
moderated list:ARM PMU PROFILING AND DEBUGGING
Em Mon, May 13, 2019 at 01:25:19PM -0700, Florian Fainelli escreveu:
> Hi all,
>
> Based on discussion about the last patch, it turned out that we can
> remove the [[:xdigit:]] wildcard entirely since get_cpuid_str() strips
> the revision bits anyway.
Thanks, applied.
- Arnaldo
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^ permalink raw reply [flat|nested] 6+ messages in thread
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2019-05-13 20:25 [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 1/3] perf vendor events arm64: Remove [[:xdigit:]] wildcard Florian Fainelli
2019-05-15 9:02 ` John Garry
2019-05-13 20:25 ` [PATCH v2 2/3] perf vendor events arm64: Map Brahma-B53 CPUID to cortex-a53 events Florian Fainelli
2019-05-13 20:25 ` [PATCH v2 3/3] perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events Florian Fainelli
2019-05-15 19:13 ` [PATCH v2 0/3] perf vendor events arm64: support for Brahma-B53, Cortex-A57/A72 Arnaldo Carvalho de Melo
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