From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,T_DKIMWL_WL_HIGH,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BCC6C282CE for ; Mon, 27 May 2019 06:08:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 40F3E216FD for ; Mon, 27 May 2019 06:08:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="nv5AEDR1"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="x743Qp7s" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 40F3E216FD Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=linuxfoundation.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pX6kCaatXLNcqy02Ezkxa1SFaUQCGkkgThW13o8jq1s=; b=nv5AEDR1ManOIA L6S9z8B5LYKWFqYNi5h9M/Vhn97aMUUL4zbRowET9Sh+uao1v9FpxzoCO6AUpuiMSo2+MVtfdtDEq uusvSrz2n/N9TDVF7Yqar225T1IZSDLGj8XjbmM0Qcg0DtSW+RddpFbDyGJr6MK79jVzXaPceSN4o IaXE8A2TCmHQb4k3ncLsdQ41HjsIKYKo1Osk1AEviQuyGHzBuPDpz/ikfow4HYKQz2ZeDubD1pkHQ pFX/O3T7TWIGvnoK5I8uEI1tN9DvnXUM9lUna3ORNYB80M/krlusrYuPIuyOWkbmHtq50AcQgA16j 2esCjgBtMsnuLU7+Hy3g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hV8oF-0007dG-FH; Mon, 27 May 2019 06:08:35 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hV8oC-0007cq-5k for linux-arm-kernel@lists.infradead.org; Mon, 27 May 2019 06:08:33 +0000 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 68B6E2075E; Mon, 27 May 2019 06:08:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1558937311; bh=whtFdsckGzCPEkaQlXnqUsZh6c2LH490Sb3G6lofpws=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=x743Qp7sU13eieitAhmmIsWD1+3gSc4TduX14oZisxlV6Aa6RK8T/hJiS3VxrZ9QR P1PmSH9O01f82B/AttB8RnGoXzbufqHoiuc8X5S9MWfkuvrG3TZDgIvOnjF0FpJWv+ yvbZ3EfZSeVuFlpF5YhQ1j3Qju0TffhuRqMRuRtQ= Date: Mon, 27 May 2019 08:08:29 +0200 From: Greg KH To: Shaokun Zhang Subject: Re: [PATCH v3 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT Message-ID: <20190527060829.GA8106@kroah.com> References: <1558922768-29155-1-git-send-email-zhangshaokun@hisilicon.com> <1558922768-29155-2-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1558922768-29155-2-git-send-email-zhangshaokun@hisilicon.com> User-Agent: Mutt/1.12.0 (2019-05-25) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190526_230832_227451_CD1FB6C2 X-CRM114-Status: GOOD ( 18.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Jeremy Linton , Zhenfa Qiu , Sudeep Holla , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote: > cache_line_size is derived from CTR_EL0.CWG field and is called mostly > for I/O device drivers. For HiSilicon certain plantform, like the > Kunpeng920 server SoC, cache line sizes are different between L1/2 > cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte, > but CTR_EL0.CWG is misreporting using L1 cache line size. > > We shall correct the right value which is important for I/O performance. > Let's update the cache line size if it is detected from DT or PPTT > information. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Sudeep Holla > Cc: Jeremy Linton > Cc: Zhenfa Qiu > Reported-by: Zhenfa Qiu > Suggested-by: Catalin Marinas > Signed-off-by: Shaokun Zhang > --- > arch/arm64/include/asm/cache.h | 6 +----- > arch/arm64/kernel/cacheinfo.c | 11 +++++++++++ > 2 files changed, 12 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h > index 926434f413fa..758af6340314 100644 > --- a/arch/arm64/include/asm/cache.h > +++ b/arch/arm64/include/asm/cache.h > @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void) > > #define __read_mostly __attribute__((__section__(".data..read_mostly"))) > > -static inline int cache_line_size(void) > -{ > - u32 cwg = cache_type_cwg(); > - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; > -} > +int cache_line_size(void); > > /* > * Read the effective value of CTR_EL0. > diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c > index 0bf0a835122f..3d54b0024246 100644 > --- a/arch/arm64/kernel/cacheinfo.c > +++ b/arch/arm64/kernel/cacheinfo.c > @@ -28,6 +28,17 @@ > #define CLIDR_CTYPE(clidr, level) \ > (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) > > +int cache_line_size(void) > +{ > + u32 cwg = cache_type_cwg(); > + > + if (coherency_max_size != 0) > + return coherency_max_size; Ah, you use it here. > + > + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; Shouldn't you set the variable if it is 0 here as well? > +} > +EXPORT_SYMBOL(cache_line_size); EXPORT_SYMBOL_GPL()? thanks, greg k-h _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel