From: Catalin Marinas <catalin.marinas@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>,
Steve Capper <steve.capper@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org, James Morse <james.morse@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64/mm: Move PTE_VALID from SW defined to HW page table entry definitions
Date: Mon, 3 Jun 2019 17:00:15 +0100 [thread overview]
Message-ID: <20190603160015.GE63283@arrakis.emea.arm.com> (raw)
In-Reply-To: <1558411587-19042-1-git-send-email-anshuman.khandual@arm.com>
On Tue, May 21, 2019 at 09:36:27AM +0530, Anshuman Khandual wrote:
> PTE_VALID signifies that the last level page table entry is valid and it is
> MMU recognized while walking the page table. This is not a software defined
> PTE bit and should not be listed like one. Just move it to appropriate
> header file.
>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Steve Capper <steve.capper@arm.com>
> Cc: Suzuki Poulose <suzuki.poulose@arm.com>
> Cc: James Morse <james.morse@arm.com>
Queued for 5.3. Thanks.
--
Catalin
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prev parent reply other threads:[~2019-06-03 16:00 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-21 4:06 [PATCH] arm64/mm: Move PTE_VALID from SW defined to HW page table entry definitions Anshuman Khandual
2019-06-03 16:00 ` Catalin Marinas [this message]
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