From: Catalin Marinas <catalin.marinas@arm.com>
To: Masayoshi Mizuma <msys.mizuma@gmail.com>
Cc: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>,
Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>,
Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org,
Zhang Lei <zhang.lei@jp.fujitsu.com>,
Robin Murphy <robin.murphy@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] arm64/mm: check cpu cache line size with non-coherent device
Date: Tue, 11 Jun 2019 19:00:07 +0100 [thread overview]
Message-ID: <20190611180007.him7md7gdcjs5cg6@mbp> (raw)
In-Reply-To: <20190611151731.6135-2-msys.mizuma@gmail.com>
On Tue, Jun 11, 2019 at 11:17:30AM -0400, Masayoshi Mizuma wrote:
> --- a/arch/arm64/mm/dma-mapping.c
> +++ b/arch/arm64/mm/dma-mapping.c
> @@ -91,10 +91,6 @@ static int __swiotlb_mmap_pfn(struct vm_area_struct *vma,
>
> static int __init arm64_dma_init(void)
> {
> - WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(),
> - TAINT_CPU_OUT_OF_SPEC,
> - "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
> - ARCH_DMA_MINALIGN, cache_line_size());
> return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC));
> }
> arch_initcall(arm64_dma_init);
> @@ -473,6 +469,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> const struct iommu_ops *iommu, bool coherent)
> {
> dev->dma_coherent = coherent;
> +
> + if (!coherent && (cache_line_size() > ARCH_DMA_MINALIGN))
> + dev_WARN(dev, "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
> + ARCH_DMA_MINALIGN, cache_line_size());
I'm ok in principle with this patch, with the minor issue that since
commit 7b8c87b297a7 ("arm64: cacheinfo: Update cache_line_size detected
from DT or PPTT") queued for 5.3 cache_line_size() gets the information
from DT or ACPI. The reason for this change is that the information is
used for performance tuning rather than DMA coherency.
You can go for a direct cache_type_cwg() check in here, unless Robin
(cc'ed) has a better idea.
--
Catalin
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next prev parent reply other threads:[~2019-06-11 18:00 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-11 15:17 [PATCH 0/2] Correct the cache line size warning Masayoshi Mizuma
2019-06-11 15:17 ` [PATCH 1/2] arm64/mm: check cpu cache line size with non-coherent device Masayoshi Mizuma
2019-06-11 18:00 ` Catalin Marinas [this message]
2019-06-11 22:02 ` Masayoshi Mizuma
2019-06-13 15:54 ` Catalin Marinas
2019-06-13 17:10 ` Robin Murphy
2019-06-11 15:17 ` [PATCH 2/2] arm64/mm: show TAINT_CPU_OUT_OF_SPEC warning if the cache size is over the spec Masayoshi Mizuma
2019-06-11 15:41 ` Catalin Marinas
2019-06-11 16:18 ` Masayoshi Mizuma
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