From: Will Deacon <will.deacon@arm.com>
To: Dave Martin <Dave.Martin@arm.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
gdb@sourceware.org, "Alan Hayward" <alan.hayward@arm.com>,
"Zhang Lei" <zhang.lei@jp.fujitsu.com>,
"Julien Grall" <julien.grall@arm.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/3] arm64/sve: Fix missing SVE/FPSIMD endianness conversions
Date: Wed, 12 Jun 2019 18:28:53 +0100 [thread overview]
Message-ID: <20190612172853.GA27039@fuggles.cambridge.arm.com> (raw)
In-Reply-To: <1560355234-25516-2-git-send-email-Dave.Martin@arm.com>
On Wed, Jun 12, 2019 at 05:00:32PM +0100, Dave Martin wrote:
> The in-memory representation of SVE and FPSIMD registers is
> different: the FPSIMD V-registers are stored as single 128-bit
> host-endian values, whereas SVE registers are stored in an
> endianness-invariant byte order.
>
> This means that the two representations differ when running on a
> big-endian host. But we blindly copy data from one representation
> to another when converting between the two, resulting in the
> register contents being unintentionally byteswapped in certain
> situations. Currently this can be triggered by the first SVE
> instruction after a syscall, for example (though the potential
> trigger points may vary in future).
>
> So, fix the conversion functions fpsimd_to_sve(), sve_to_fpsimd()
> and sve_sync_from_fpsimd_zeropad() to swab where appropriate.
>
> There is no common swahl128() or swab128() that we could use here.
> Maybe it would be worth making this generic, but for now add a
> simple local hack.
>
> Since the byte order differences are exposed in ABI, also clarify
> the docuentation.
>
> Fixes: bc0ee4760364 ("arm64/sve: Core task context handling")
> Fixes: 8cd969d28fd2 ("arm64/sve: Signal handling support")
> Fixes: 43d4da2c45b2 ("arm64/sve: ptrace and ELF coredump support")
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Thanks, Dave. I've picked this one up and pushed it out to our fixes branch
for 5.2. I assume Catalin will take the other two for 5.3. It's probably
worth proposing some generic 128-bit swab functions too, in case there's any
interest (in which case we could drop our local implementation later on).
Cheers,
Will
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next prev parent reply other threads:[~2019-06-12 17:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-12 16:00 [PATCH v2 0/3] arm64/sve: Fix mutating register endianness on big-endian Dave Martin
2019-06-12 16:00 ` [PATCH v2 1/3] arm64/sve: Fix missing SVE/FPSIMD endianness conversions Dave Martin
2019-06-12 17:28 ` Will Deacon [this message]
2019-06-27 13:51 ` Catalin Marinas
2019-06-27 15:18 ` Dave Martin
2019-06-12 17:46 ` Julien Grall
2019-06-13 9:22 ` Will Deacon
2019-06-13 10:00 ` Dave Martin
2019-06-13 10:17 ` Will Deacon
2019-06-13 10:20 ` Dave Martin
2019-06-12 16:00 ` [PATCH v2 2/3] arm64/sve: Factor out FPSIMD to SVE state conversion Dave Martin
2019-06-20 13:45 ` Julien Grall
2019-07-22 10:31 ` Catalin Marinas
2019-06-12 16:00 ` [PATCH v2 3/3] arm64/sve: Fix a couple of magic numbers for the Z-reg count Dave Martin
2019-06-20 13:43 ` Julien Grall
2019-07-22 10:32 ` Catalin Marinas
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