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[198.145.64.163]) by smtp.gmail.com with ESMTPSA id s12sm5323358pji.30.2019.06.15.06.59.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 15 Jun 2019 06:59:35 -0700 (PDT) Date: Sat, 15 Jun 2019 06:59:33 -0700 From: Kees Cook To: Ard Biesheuvel Subject: Re: [RFC] Disable lockref on arm64 Message-ID: <201906150654.FF4400F7C8@keescook> References: <20190522160417.GF7876@fuggles.cambridge.arm.com> <20190612040933.GA18848@dc5-eodlnx05.marvell.com> <20190612093151.GA11554@brain-police> <20190614070914.GA21961@dc5-eodlnx05.marvell.com> <20190614095846.GC10506@fuggles.cambridge.arm.com> <20190614103850.GG10659@fuggles.cambridge.arm.com> <201906142026.1BC27EDB1E@keescook> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190615_065937_180072_5B5E76F7 X-CRM114-Status: GOOD ( 12.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "catalin.marinas@arm.com" , Jan Glauber , Will Deacon , "linux-kernel@vger.kernel.org" , Jayachandran Chandrasekharan Nair , Linus Torvalds , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Jun 15, 2019 at 10:47:19AM +0200, Ard Biesheuvel wrote: > remaining question Will had was whether it makes sense to do the > condition checks before doing the actual store, to avoid having a time > window where the refcount assumes its illegal value. Since arm64 does > not have memory operands, the instruction count wouldn't change, but > it will definitely result in a performance hit on out-of-order CPUs. What do the races end up looking like? Is it possible to have two threads ordered in a way that a second thread could _un_saturate a counter? CPU 1 CPU 2 inc() load INT_MAX-1 about to overflow? yes dec() load INT_MAX-1 set to INT_MAX set to INT_MAX-2 Or would you use the same INT_MIN/2 saturation point done on x86? As for performance, it should be easy to measure with the LKDTM test to find out exactly the differences. -- Kees Cook _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel