From: <alpawi@amazon.com>
Cc: Benjamin Herrenschmidt <benh@amazon.com>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Gregory Clement <gregory.clement@bootlin.com>,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Linus Walleij <linus.walleij@linaro.org>,
Patrick Williams <alpawi@amazon.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: [PATCH 0/2] pinctl: armada-37xx: fix for pins 32+
Date: Tue, 18 Jun 2019 11:01:03 -0500 [thread overview]
Message-ID: <20190618160105.26343-1-alpawi@amazon.com> (raw)
From: Patrick Williams <alpawi@amazon.com>
The 37xx GPIO config registers are only 32 bits long and
span 2 registers for the NB GPIO controller. The function
to calculate the offset was missing the increase to the
config register.
I have tested both raw gpio access and interrupts using
libgpiod utilities on an Espressonbin.
The first patch is a simple rename of a function because
the original name implied it was doing IO itself ("update
reg"). This patch could be dropped if undesired.
The second patch contains the fix for GPIOs 32+.
Patrick Williams (2):
pinctrl: armada-37xx: rename reg-offset function
pinctrl: armada-37xx: fix control of pins 32 and up
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
--
2.17.2 (Apple Git-113)
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next reply other threads:[~2019-06-18 16:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-18 16:01 alpawi [this message]
2019-06-18 16:01 ` [PATCH 1/2] pinctrl: armada-37xx: rename reg-offset function alpawi
2019-06-18 16:01 ` [PATCH 2/2] pinctrl: armada-37xx: fix control of pins 32 and up alpawi
2019-10-01 15:46 ` [PATCH v2] " Patrick Williams
2019-10-04 21:54 ` Linus Walleij
2019-06-25 12:31 ` [PATCH 0/2] pinctl: armada-37xx: fix for pins 32+ Linus Walleij
2019-06-25 13:38 ` Gregory CLEMENT
2019-06-25 14:25 ` Patrick Williams
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