From: Andrew Murray <andrew.murray@arm.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: coresight@lists.linaro.org, Sudeep Holla <sudeep.holla@arm.com>,
stable@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Mike Leach <mike.leach@linaro.org>
Subject: [PATCH v2 2/5] coresight: etm4x: use explicit barriers on enable/disable
Date: Thu, 27 Jun 2019 09:35:22 +0100 [thread overview]
Message-ID: <20190627083525.37463-3-andrew.murray@arm.com> (raw)
In-Reply-To: <20190627083525.37463-1-andrew.murray@arm.com>
Synchronization is recommended before disabling the trace registers
to prevent any start or stop points being speculative at the point
of disabling the unit (section 7.3.77 of ARM IHI 0064D).
Synchronization is also recommended after programming the trace
registers to ensure all updates are committed prior to normal code
resuming (section 4.3.7 of ARM IHI 0064D).
Let's ensure these syncronization points are present in the code
and clearly commented.
Note that we could rely on the barriers in CS_LOCK and
coresight_disclaim_device_unlocked or the context switch to user
space - however coresight may be of use in the kernel.
Signed-off-by: Andrew Murray <andrew.murray@arm.com>
CC: stable@vger.kernel.org
---
drivers/hwtracing/coresight/coresight-etm4x.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index c89190d464ab..68e8e3954cef 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -188,6 +188,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
dev_err(etm_dev,
"timeout while waiting for Idle Trace Status\n");
+ /* As recommended by 4.3.7 of ARM IHI 0064D */
+ dsb(sy);
+ isb();
+
done:
CS_LOCK(drvdata->base);
@@ -454,7 +458,8 @@ static void etm4_disable_hw(void *info)
control &= ~0x1;
/* make sure everything completes before disabling */
- mb();
+ /* As recommended by 7.3.77 of ARM IHI 0064D */
+ dsb(sy);
isb();
writel_relaxed(control, drvdata->base + TRCPRGCTLR);
--
2.21.0
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next prev parent reply other threads:[~2019-06-27 8:35 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 8:35 [PATCH v2 0/5] coresight: etm4x: save/restore ETMv4 context across CPU low power states Andrew Murray
2019-06-27 8:35 ` [PATCH v2 1/5] coresight: etm4x: remove superfluous setting of os_unlock Andrew Murray
2019-06-27 8:35 ` Andrew Murray [this message]
2019-06-27 9:16 ` [PATCH v2 2/5] coresight: etm4x: use explicit barriers on enable/disable Suzuki K Poulose
2019-06-27 11:41 ` Andrew Murray
2019-06-28 2:45 ` Leo Yan
2019-06-28 8:35 ` Andrew Murray
2019-06-28 8:51 ` Leo Yan
2019-06-28 9:00 ` Andrew Murray
2019-06-28 9:41 ` Leo Yan
2019-07-01 8:58 ` Suzuki K Poulose
2019-07-01 9:59 ` Leo Yan
2019-06-27 8:35 ` [PATCH v2 3/5] coresight: etm4x: use module_param instead of module_param_named Andrew Murray
2019-06-27 8:35 ` [PATCH v2 4/5] coresight: etm4x: improve clarity of etm4_os_unlock comment Andrew Murray
2019-06-27 8:35 ` [PATCH v2 5/5] coresight: etm4x: save/restore state across CPU low power states Andrew Murray
2019-06-27 14:25 ` Mike Leach
2019-06-27 14:55 ` Andrew Murray
2019-06-27 16:01 ` Suzuki K Poulose
2019-07-08 14:35 ` Andrew Murray
2019-06-28 8:07 ` Leo Yan
2019-06-28 8:53 ` Andrew Murray
2019-06-28 9:12 ` Leo Yan
2019-06-28 9:22 ` Andrew Murray
2019-07-01 2:07 ` Leo Yan
2019-07-01 9:34 ` Andrew Murray
2019-07-01 9:48 ` Leo Yan
2019-07-01 9:54 ` Andrew Murray
2019-07-01 10:14 ` Leo Yan
2019-07-04 10:21 ` Andrew Murray
2019-07-04 14:27 ` Mathieu Poirier
2019-07-05 1:52 ` Leo Yan
2019-07-01 13:15 ` Suzuki K Poulose
2019-07-04 9:59 ` Andrew Murray
2019-07-03 21:21 ` Mathieu Poirier
2019-07-04 10:06 ` Andrew Murray
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