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From: Joakim Zhang <qiangqing.zhang@nxp.com>
To: "robin.murphy@arm.com" <robin.murphy@arm.com>,
	"will@kernel.org" <will@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	Frank Li <frank.li@nxp.com>
Cc: Joakim Zhang <qiangqing.zhang@nxp.com>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	dl-linux-imx <linux-imx@nxp.com>
Subject: [PATCH V4 2/2] Documentation: admin-guide: perf: add i.MX8 ddr pmu user doc
Date: Wed, 31 Jul 2019 10:46:13 +0000	[thread overview]
Message-ID: <20190731104351.3117-2-qiangqing.zhang@nxp.com> (raw)
In-Reply-To: <20190731104351.3117-1-qiangqing.zhang@nxp.com>

Add i.MX8 ddr pmu user doc.

ChangeLog:
V1 -> V4:
	* new add in V4.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
 Documentation/admin-guide/perf/imx-ddr.rst | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/admin-guide/perf/imx-ddr.rst

diff --git a/Documentation/admin-guide/perf/imx-ddr.rst b/Documentation/admin-guide/perf/imx-ddr.rst
new file mode 100644
index 000000000000..9beb47e86c9c
--- /dev/null
+++ b/Documentation/admin-guide/perf/imx-ddr.rst
@@ -0,0 +1,30 @@
+====================================================
+Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
+====================================================
+
+There are no performance counters inside the DRAM controller, so performance
+signals are brought out to the edge of the controller where a set of 4 x 32 bit
+counters is implemented. This is controlled by the Performance log on parameter
+which causes a large number of PERF signals to be generated.
+
+Selection of the value for each counter is done via the config registiers. There
+is one register for each counter. Counter 0 is special in that it always counts
+“time” and when expired causes a lock on itself and the other counters and an
+interrupt ie enable of counter 0 is a global function.
+
+The "format" directory describes format of the config (event ID) and config1
+(AXI ID filter) fields of the perf_event_attr structure, see /sys/bus/event_source/
+devices/imx8_ddr0/format/. The "events" directory describes the events types
+hardware supported that can be used with perf tool, see /sys/bus/event_source/
+devices/imx8_ddr0/events/.
+
+AXI filtering is used by CSV modes 0x41 (axi-id-read event) and 0x42 (axi-id-write
+event) to count reads or writes matching filter setting. Read and write AXI ID
+filter must have the same value if you want to specify them at the same time as
+this filter is shared between counters.
+
+Example for perf tool use::
+
+        perf stat -e imx8_ddr0/cycles/ sleep 1
+        perf stat -e imx8_ddr0/read/,imx8_ddr0/write/ sleep 1
+        perf stat -e imx8_ddr0/axi-id-read,axi_id=0xMMMMDDDD/,imx8_ddr0/axi-id-write,axi_id=0xMMMMDDDD/ sleep 1
-- 
2.17.1

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  reply	other threads:[~2019-07-31 10:46 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-31 10:46 [PATCH V4 1/2] perf: imx8_ddr_perf: add AXI ID filter support Joakim Zhang
2019-07-31 10:46 ` Joakim Zhang [this message]
2019-07-31 12:36 ` Robin Murphy
2019-08-01  5:25   ` Joakim Zhang
2019-08-01  9:59     ` Robin Murphy
2019-08-02  7:19       ` Joakim Zhang
2019-08-05 10:33         ` Joakim Zhang
2019-08-08  6:11           ` Joakim Zhang

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