From: Catalin Marinas <catalin.marinas@arm.com>
To: Julien Thierry <julien.thierry.kdev@gmail.com>
Cc: Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
Oleg Nesterov <oleg@redhat.com>,
linux-arm-kernel@lists.infradead.org, julien.thierry@arm.com
Subject: Re: [PATCH] arm64: Lower priority mask for GIC_PRIO_IRQON
Date: Wed, 31 Jul 2019 18:22:38 +0100 [thread overview]
Message-ID: <20190731172238.GG17773@arrakis.emea.arm.com> (raw)
In-Reply-To: <1564412266-9790-1-git-send-email-julien.thierry.kdev@gmail.com>
On Mon, Jul 29, 2019 at 03:57:46PM +0100, Julien Thierry wrote:
> On a system with two security states, if SCR_EL3.FIQ is set, non-secure
> IRQ priorities get shifted to fit the secure view but priority masks
> aren't.
>
> On such system, it turns out that GIC_PRIO_IRQON masks the priority of
> normal interrupts, which obviously ends up in a hang.
>
> Increase GIC_PRIO_IRQON value (i.e. lower priority) to make sure
> interrupts are not blocked by it.
>
> Fixes: bd82d4bd21880b7c ("arm64: Fix incorrect irqflag restore for
> priority masking")
> Signed-off-by: Julien Thierry <julien.thierry.kdev@gmail.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Oleg Nesterov <oleg@redhat.com>
> Cc: Marc Zyngier <maz@kernel.org>
I queued this through the arm64 for-next/fixes tree. Thanks.
--
Catalin
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prev parent reply other threads:[~2019-07-31 17:22 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-29 14:57 [PATCH] arm64: Lower priority mask for GIC_PRIO_IRQON Julien Thierry
2019-07-29 15:14 ` Julien Thierry
2019-07-29 16:39 ` Marc Zyngier
2019-07-31 17:22 ` Catalin Marinas [this message]
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