From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA89EC433FF for ; Wed, 7 Aug 2019 13:00:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8CA2421BE3 for ; Wed, 7 Aug 2019 13:00:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ShC3o65w" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8CA2421BE3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=a22nq2mCEW/EU/FlJUEKvWHDBu6IwMhz9rTGCy+8jFA=; b=ShC3o65wBn6ZID 0RpmOXjdk/85cbtl/riV1GjpdYJqmEQcn99a3LUQmN7j79fZQ8rA78Q6arUCiGyy8QI/tGij2jOcX tEj7SaeYdM+/na+HfWuHvbtTUozpd53PTAVrH43CE7gyQAzav8k2NzWLyvhpWbLNgU3sTRRZE3IAb OCRrBDw1gg3BqE8IyxzKrihasGqdDI53b1I2A2xC7Re76a61WDtVuDLZAqEkHsbwsxZJLOGcsjmA4 46OUDOmpJdemuZHLuP6CAqTXJtoOMdjXR+XV2CuFxYiscdaO7XUZudcp4mWCsURlqI5KdR8VO05h/ DNeZqzEESFQLBk62TNTA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hvLYc-0003KD-1z; Wed, 07 Aug 2019 13:00:46 +0000 Received: from hch by bombadil.infradead.org with local (Exim 4.92 #3 (Red Hat Linux)) id 1hvLYZ-0003Jq-N1; Wed, 07 Aug 2019 13:00:43 +0000 Date: Wed, 7 Aug 2019 06:00:43 -0700 From: Christoph Hellwig To: "Koenig, Christian" Subject: Re: [PATCH] drm/amdgpu: replace readq/writeq with atomic64 operations Message-ID: <20190807130043.GA6023@infradead.org> References: <20190807025640.682-1-tao.zhou1@amd.com> <20190807070834.GA24792@infradead.org> <20190807104104.GA18773@infradead.org> <18cd9fa5-2d87-2f41-b5fa-927b9790287d@amd.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <18cd9fa5-2d87-2f41-b5fa-927b9790287d@amd.com> User-Agent: Mutt/1.11.4 (2019-03-13) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "linux-arm-kernel@lists.infradead.org" , "kernel-build-reports@lists.linaro.org" , "Zhou1, Tao" , "amd-gfx@lists.freedesktop.org" , Christoph Hellwig , "broonie@kernel.org" , "linux-next@vger.kernel.org" , "Deucher, Alexander" , "akpm@linux-foundation.org" , "Li, Dennis" , "Zhang, Hawking" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 07, 2019 at 10:55:01AM +0000, Koenig, Christian wrote: > >> Essentially writeq/readq doesn't seems to be available on all > >> architectures either. > > writeq/readq are provided whenever the CPU actually supports 64-bit > > atomic loads and stores. > > Is there a config option which we can make the driver depend on? > > I mean that ARM doesn't support 64bit atomic loads and stores on MMIO is > quite a boomer for us. The model is to cheack if readq/writeq are defined, and if not to include the one of io-64-nonatomic-hi-lo.h or io-64-nonatomic-lo-hi.h. The reason for that is that hardware is supposed to be able to deal with two 32-bit writes, but it depends on the hardware if the lower or upper half is what commits the write. The only 32-bit platform that claims support for readq/writeq is sh, and I have doubts if that actually works as expected. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel