From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org,
Nagarjuna Kristam <nkristam@nvidia.com>,
linux-arm-kernel@lists.infradead.org,
Jon Hunter <jonathanh@nvidia.com>
Subject: [PATCH 3/7] soc/tegra: fuse: Add cell information
Date: Fri, 30 Aug 2019 00:19:07 +0200 [thread overview]
Message-ID: <20190829221911.24876-4-thierry.reding@gmail.com> (raw)
In-Reply-To: <20190829221911.24876-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
Create nvmem cells for all the fuses currently used by consumers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/soc/tegra/fuse/fuse-tegra.c | 90 +++++++++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index 3ce2138b278b..c6c6a7746046 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -86,6 +86,94 @@ static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
return 0;
}
+static const struct nvmem_cell_info tegra_fuse_cells[] = {
+ {
+ .name = "tsensor-cpu1",
+ .offset = 0x084,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-cpu2",
+ .offset = 0x088,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-cpu0",
+ .offset = 0x098,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "xusb-pad-calibration",
+ .offset = 0x0f0,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-cpu3",
+ .offset = 0x12c,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "sata-calibration",
+ .offset = 0x124,
+ .bytes = 1,
+ .bit_offset = 0,
+ .nbits = 2,
+ }, {
+ .name = "tsensor-gpu",
+ .offset = 0x154,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-mem0",
+ .offset = 0x158,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-mem1",
+ .offset = 0x15c,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-pllx",
+ .offset = 0x160,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-common",
+ .offset = 0x180,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-realignment",
+ .offset = 0x1fc,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "gpu-calibration",
+ .offset = 0x204,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "xusb-pad-calibration-ext",
+ .offset = 0x250,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ },
+};
+
static int tegra_fuse_probe(struct platform_device *pdev)
{
void __iomem *base = fuse->base;
@@ -127,6 +215,8 @@ static int tegra_fuse_probe(struct platform_device *pdev)
nvmem.name = "fuse";
nvmem.id = -1;
nvmem.owner = THIS_MODULE;
+ nvmem.cells = tegra_fuse_cells;
+ nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
nvmem.type = NVMEM_TYPE_OTP;
nvmem.read_only = true;
nvmem.root_only = true;
--
2.22.0
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next prev parent reply other threads:[~2019-08-29 22:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 22:19 [PATCH 0/7] Replace Tegra FUSE API by nvmem API Thierry Reding
2019-08-29 22:19 ` [PATCH 1/7] soc/tegra: fuse: Restore base on sysfs failure Thierry Reding
2019-08-29 22:19 ` [PATCH 2/7] soc/tegra: fuse: Implement nvmem device Thierry Reding
2019-08-29 22:19 ` Thierry Reding [this message]
2019-08-29 22:19 ` [PATCH 4/7] soc/tegra: fuse: Register cell lookups for compatibility Thierry Reding
2019-08-29 22:19 ` [PATCH 5/7] drm/nouveau: tegra: Use nvmem API Thierry Reding
2019-08-29 22:19 ` [PATCH 6/7] phy: tegra: xusb: " Thierry Reding
2019-08-29 22:19 ` [PATCH 7/7] thermal: tegra: " Thierry Reding
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